1 diff --git a/drivers/ata/sata_brcmstb.c b/drivers/ata/sata_brcmstb.c
2 index 7ba20e0..1e2e947 100644
3 --- a/drivers/ata/sata_brcmstb.c
4 +++ b/drivers/ata/sata_brcmstb.c
5 @@ -330,6 +330,22 @@ static void brcm_EnableOOBWindowFix(void __iomem *mmio_base, int port)
6 mdio_write_reg(mmio_base, port, 0x0D, sval);
9 +static void brcm_Enable256AlignDetection(void __iomem *mmio_base, int port)
12 + void __iomem *port_mmio;
14 + port_mmio = PORT_BASE(mmio_base, port);
16 + tmp32 = readl(port_mmio + K2_SATA_SICR1_OFFSET);
17 + tmp32 |= 0x08000000;
18 + writel(tmp32, port_mmio + K2_SATA_SICR1_OFFSET);
20 + tmp32 = readl(port_mmio + K2_SATA_SICR2_OFFSET);
21 + tmp32 |= 0x00800000;
22 + writel(tmp32, port_mmio + K2_SATA_SICR2_OFFSET);
25 static void brcm_AnalogReset(void __iomem *mmio_base, int port)
28 @@ -385,6 +401,8 @@ static void brcm_InitSata_1_5Gb(void __iomem *mmio_base, int port)
29 brcm_SetPllTxRxCtrl(mmio_base, port);
30 brcm_EnableOOBWindowFix(mmio_base, port);
32 + brcm_Enable256AlignDetection(mmio_base, port);
35 #ifdef CONFIG_BRCM_SATA_75MHZ_PLL
36 /* use 75Mhz PLL clock */
37 @@ -446,6 +464,8 @@ static void brcm_InitSata2_3Gb(void __iomem *mmio_base, int port)
38 brcm_SetPllTxRxCtrl(mmio_base, port);
39 brcm_EnableOOBWindowFix(mmio_base, port);
41 + brcm_Enable256AlignDetection(mmio_base, port);
44 #ifdef CONFIG_BRCM_SATA_75MHZ_PLL
45 /* use 75Mhz PLL clock */
46 @@ -1135,7 +1155,9 @@ static int k2_sata_resume(struct device *dev)
49 ata_for_each_link(link, ap, EDGE) {
50 + spin_unlock_irqrestore(&hp->lock, flags);
51 sata_std_hardreset(link, NULL, 1000);
52 + spin_lock_irqsave(&hp->lock, flags);