+diff --git a/arch/mips/brcmstb/board.c b/arch/mips/brcmstb/board.c
+index ab1cb65..2875cf5 100644
+--- a/arch/mips/brcmstb/board.c
++++ b/arch/mips/brcmstb/board.c
+@@ -311,7 +311,7 @@ void __init board_pinmux_setup(void)
+ PINMUX(7, gpio_035, 1); /* UARTB RX */
+ PINMUX(7, gpio_038, 1); /* UARTC TX */
+ PINMUX(7, gpio_039, 1); /* UARTC RX */
+-
++#if 0
+ PINMUX(9, gpio_054, 3); /* MII */
+ PINMUX(9, gpio_055, 3);
+ PINMUX(9, gpio_056, 3);
+@@ -330,6 +330,7 @@ void __init board_pinmux_setup(void)
+ PINMUX(10, gpio_070, 3);
+ PINMUX(10, gpio_071, 3);
+ PINMUX(10, gpio_072, 3);
++#endif
+
+ #elif defined(CONFIG_BCM7340)
+
+@@ -718,15 +719,13 @@ void __init board_get_ram_size(unsigned long *dram0_mb, unsigned long *dram1_mb)
+
+ static struct mtd_partition fixed_partition_map[] = {
+ /* name offset size */
+- { name: "rootfs", offset: 0, size:0x1F200000 /* DEFAULT_ROOTFS_SIZE*/ }, /* rootfs is total nand size - 6 M Bytes. referr to cfe. bcm97335_devs.c */
+- { name: "kernel", offset: 0x1F200000, size: 4<<20 },
+- { name: "boot", offset: 0x1F600000, size: 4<<20 },
+- { name: "splash", offset: 0x1FA00000, size: 2<<20 },
+- { name: "cfe", offset: 0x1FC00000, size: 1<<20 },
+- { name: "mac", offset: 0x1FD00000, size: 1<<19 },
+- { name: "env", offset: 0x1FD80000, size: 1<<19 },
+- { name: "nvm", offset: 0x1FE00000, size: 1<<20 },
+- { name: "data", offset: 0x20000000, size: 0x1FC00000 },
++ { name: "rootfs", offset: 0, size: (128-4-2-3-1)<<20 }, /* rootfs is total nand size - 6 M Bytes. referr to cfe. bcm97335_devs.c */
++ { name: "kernel", offset: 0x07600000, size: 4<<20 },
++ { name: "boot", offset: 0x07a00000, size: 2<<20 },
++ { name: "cfe", offset: 0x07C00000, size: 1<<20 },
++ { name: "mac", offset: 0x07D00000, size: 1<<19 },
++ { name: "env", offset: 0x07D80000, size: 1<<19 },
++ { name: "nvm", offset: 0x07E00000, size: 1<<20 },
+ /* BBT 1MB not mountable by anyone */
+ /* { name: "data", offset: 0x20000000, size: 0 },*/
+ /* Add 1 extra place-holder partition for splash, and a safety guard element */
+diff --git a/drivers/mtd/brcmnand/brcmnand_base.c b/drivers/mtd/brcmnand/brcmnand_base.c
+index 22035af..b54bc29 100644
+--- a/drivers/mtd/brcmnand/brcmnand_base.c
++++ b/drivers/mtd/brcmnand/brcmnand_base.c
+@@ -226,8 +226,8 @@ static brcmnand_chip_Id brcmnand_chips[] = {
+ .options = NAND_USE_FLASH_BBT, /* Use BBT on flash */
+ .idOptions = 0,
+ //| NAND_COMPLEX_OOB_WRITE /* Write data together with OOB for write_oob */
+- .timing1 = 0, //00070000,
+- .timing2 = 0,
++ .timing1 = 0x4232222D,
++ .timing2 = 0x00000D94,
+ .nop=8,
+ .ctrlVersion = 0, /* THT Verified on data-sheet 7/10/08: Allows 4 on main and 4 on OOB */
+ },
+@@ -7553,10 +7553,7 @@ brcmnand_decode_config(struct brcmnand_chip* chip, uint32_t nand_config)
+ chip->blockSize = 2048 << 10;
+ break;
+ #endif
+- case BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB:
+- chip->blockSize = 256 << 10;
+- break;
+- case BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB:
++ case BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB:
+ chip->blockSize = 512 << 10;
+ break;
+ case BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB:
+@@ -7772,7 +7769,7 @@ is_ecc_strong(int registerEcc, int requiredEcc)
+ }
+
+
+-
++#if CONFIG_MTD_BRCMNAND_VERSION >= CONFIG_MTD_BRCMNAND_VERS_3_0
+ static void
+ brcmnand_set_acccontrol(struct brcmnand_chip * chip , unsigned int chipSelect,
+ uint32_t pageSize, uint16_t oobSizePerPage, int reqEcc, int codeWorkSize, int nbrBitsPerCell)
+@@ -7928,7 +7925,7 @@ PRINTK("%s: gAccControl[CS=%d]=%08x, ACC=%08lx\n",
+ #endif
+ }
+ }
+-
++#endif
+
+ static void
+ brcmnand_read_id(struct mtd_info *mtd, unsigned int chipSelect, unsigned long* dev_id)
+@@ -8005,6 +8002,7 @@ printk("After: NandSelect=%08x, nandConfig=%08x\n", nandSelect, nandConfig);
+ }
+
+
++#if CONFIG_MTD_BRCMNAND_VERSION >= CONFIG_MTD_BRCMNAND_VERS_3_0
+ /*
+ * Type-1 ID string, called from brcmnand_probe with the following condition
+ * if ((brcmnand_chips[i].idOptions & BRCMNAND_ID_HAS_BYTE4) &&
+@@ -8202,7 +8200,9 @@ PRINTK("nandConfigChipSize = %04x\n", nandConfigChipSize);
+
+ return nand_config;
+ }
++#endif
+
++#if CONFIG_MTD_BRCMNAND_VERSION >= CONFIG_MTD_BRCMNAND_VERS_3_0
+
+ /*
+ * Type-2 ID string, called from brcmnand_probe with the following condition
+@@ -8372,8 +8372,9 @@ PRINTK("Required ECC level = %d, devIdExt=%08x, eccShift=%02x, sector Size=%d\n"
+
+ return nand_config;
+ }
++#endif
+
+-
++#if CONFIG_MTD_BRCMNAND_VERSION >= CONFIG_MTD_BRCMNAND_VERS_3_0
+ /*
+ * Type-2 ID string, called from brcmnand_probe with the following condition
+ * if ((brcmnand_chips[i].idOptions & BRCMNAND_ID_EXT_BYTES_TYPE2) ==
+@@ -8519,6 +8520,7 @@ PRINTK("Updating Config Reg on CS%1d: Block & Page Size: After: %08x\n", chip->c
+
+ return nand_config;
+ }
++#endif
+
+
+ #if CONFIG_MTD_BRCMNAND_VERSION >= CONFIG_MTD_BRCMNAND_VERS_4_0
+@@ -9074,7 +9076,7 @@ static int brcmnand_probe(struct mtd_info *mtd, unsigned int chipSelect)
+ for (i=0; i < BRCMNAND_MAX_CHIPS; i++) {
+ if (brcmnand_dev_id == brcmnand_chips[i].chipId
+ && brcmnand_maf_id == brcmnand_chips[i].mafId) {
+-
++#if CONFIG_MTD_BRCMNAND_VERSION >= CONFIG_MTD_BRCMNAND_VERS_3_0
+ /* No ambiguity in ID#3,4,5 */
+ if (brcmnand_chips[i].chipId345[0] == 0x0
+ && brcmnand_chips[i].chipId345[1] == 0x0
+@@ -9113,6 +9115,15 @@ static int brcmnand_probe(struct mtd_info *mtd, unsigned int chipSelect)
+ }
+ /* Else not match */
+ }
++#else
++ if (brcmnand_chips[i].chipId345[0] == 0x0
++ && brcmnand_chips[i].chipId345[1] == 0x0
++ && brcmnand_chips[i].chipId345[2] == 0x0) {
++ foundInIdTable = 1;
++ break;
++ }
++
++#endif
+ }
+ }
+
+@@ -9312,7 +9323,7 @@ static int brcmnand_probe(struct mtd_info *mtd, unsigned int chipSelect)
+ printk("%s: Ecc level set to %d, sectorSize=%d from ID table\n", __FUNCTION__, chip->reqEccLevel, chip->eccSectorSize);
+ }
+ }
+-
++#if CONFIG_MTD_BRCMNAND_VERSION >= CONFIG_MTD_BRCMNAND_VERS_3_0
+ /* ID not in table, and no CONFIG REG was passed at command line */
+ else if (!skipIdLookup && !foundInIdTable) {
+ uint32_t acc;
+@@ -9339,6 +9350,7 @@ printk("%s: Ecc level set to %d, sectorSize=%d from ID table\n", __FUNCTION__, c
+ printk("Spare Area Size = %dB/512B\n", chip->eccOobSize);
+
+ }
++#endif
+ }
+
+ /*
+@@ -9355,10 +9367,11 @@ printk("%s: Ecc level set to %d, sectorSize=%d from ID table\n", __FUNCTION__, c
+ // Also works for dummy entries, but no adjustments possible
+ brcmnand_adjust_timings(chip, &brcmnand_chips[i]);
+
++#if CONFIG_MTD_BRCMNAND_VERSION >= CONFIG_MTD_BRCMNAND_VERS_3_0
+ // Adjust perchip NAND ACC CONTROL
+ // updateInternalData = not ONFI .or. not in ID table
+ brcmnand_adjust_acccontrol(chip, isONFI, foundInIdTable, i);
+-
++#endif
+
+ /* Flash device information */
+ brcmnand_print_device_info(&brcmnand_chips[i], mtd);