* Rename recipe.
--- /dev/null
+From 901b05b33b8ca924bab3fa63ef3fd6dcb123e318 Mon Sep 17 00:00:00 2001
+From: Hugo Villeneuve <hugo@hugovil.com>
+Date: Sat, 24 Jan 2009 17:57:30 -0800
+Subject: [PATCH 01/12] USB: musb cppi bugfixes
+
+These compilation errors are related to incorrect
+debugging macro and variable names and generated the
+following errors:
+
+ drivers/usb/musb/cppi_dma.c:437:5: warning: "MUSB_DEBUG" is not defined
+ drivers/usb/musb/cppi_dma.c: In function 'cppi_next_rx_segment':
+ drivers/usb/musb/cppi_dma.c:884: error: 'debug' undeclared (first use in this function)
+
+Signed-off-by: Hugo Villeneuve <hugo@hugovil.com>
+Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+---
+ drivers/usb/musb/cppi_dma.c | 9 +++++++--
+ 1 files changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
+index 5ad6d08..d8d5345 100644
+--- a/drivers/usb/musb/cppi_dma.c
++++ b/drivers/usb/musb/cppi_dma.c
+@@ -9,6 +9,7 @@
+ #include <linux/usb.h>
+
+ #include "musb_core.h"
++#include "musb_debug.h"
+ #include "cppi_dma.h"
+
+
+@@ -423,6 +424,7 @@ cppi_rndis_update(struct cppi_channel *c, int is_rx,
+ }
+ }
+
++#ifdef CONFIG_USB_MUSB_DEBUG
+ static void cppi_dump_rxbd(const char *tag, struct cppi_descriptor *bd)
+ {
+ pr_debug("RXBD/%s %08x: "
+@@ -431,10 +433,11 @@ static void cppi_dump_rxbd(const char *tag, struct cppi_descriptor *bd)
+ bd->hw_next, bd->hw_bufp, bd->hw_off_len,
+ bd->hw_options);
+ }
++#endif
+
+ static void cppi_dump_rxq(int level, const char *tag, struct cppi_channel *rx)
+ {
+-#if MUSB_DEBUG > 0
++#ifdef CONFIG_USB_MUSB_DEBUG
+ struct cppi_descriptor *bd;
+
+ if (!_dbg_level(level))
+@@ -881,12 +884,14 @@ cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket)
+ bd->hw_options |= CPPI_SOP_SET;
+ tail->hw_options |= CPPI_EOP_SET;
+
+- if (debug >= 5) {
++#ifdef CONFIG_USB_MUSB_DEBUG
++ if (_dbg_level(5)) {
+ struct cppi_descriptor *d;
+
+ for (d = rx->head; d; d = d->next)
+ cppi_dump_rxbd("S", d);
+ }
++#endif
+
+ /* in case the preceding transfer left some state... */
+ tail = rx->last_processed;
+--
+1.5.4.5
+
--- /dev/null
+From f090919d8c0d1ecb0df6148ff34b6c20d4fb4ba3 Mon Sep 17 00:00:00 2001
+From: Hugo Villeneuve <hugo@hugovil.com>
+Date: Thu, 5 Mar 2009 14:35:56 -0500
+Subject: [PATCH 02/12] ARM: Mark unsupported syscalls as IGNORE
+
+Signed-off-by: Hugo Villeneuve <hugo@hugovil.com>
+---
+ scripts/checksyscalls.sh | 7 +++++++
+ 1 files changed, 7 insertions(+), 0 deletions(-)
+
+diff --git a/scripts/checksyscalls.sh b/scripts/checksyscalls.sh
+index 60d00d1..2a75819 100755
+--- a/scripts/checksyscalls.sh
++++ b/scripts/checksyscalls.sh
+@@ -109,6 +109,13 @@ cat << EOF
+ #define __IGNORE_getpmsg
+ #define __IGNORE_putpmsg
+ #define __IGNORE_vserver
++
++/* Remove some warnings for ARM target. */
++#define __IGNORE_fadvise64
++#define __IGNORE_migrate_pages
++#define __IGNORE_pselect6
++#define __IGNORE_ppoll
++#define __IGNORE_epoll_pwait
+ EOF
+ }
+
+--
+1.5.4.5
+
--- /dev/null
+From 33beaeec0dfec8cc5bf7a88f524a2a1f41fa30ba Mon Sep 17 00:00:00 2001
+From: Hugo Villeneuve <hugo@hugovil.com>
+Date: Thu, 5 Mar 2009 14:45:19 -0500
+Subject: [PATCH 03/12] Add macros for enabling a UART
+
+Signed-off-by: Hugo Villeneuve <hugo@hugovil.com>
+---
+ arch/arm/mach-davinci/include/mach/serial.h | 5 +++++
+ 1 files changed, 5 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
+index de7c667..d77d25b 100644
+--- a/arch/arm/mach-davinci/include/mach/serial.h
++++ b/arch/arm/mach-davinci/include/mach/serial.h
+@@ -30,6 +30,11 @@ struct davinci_uart_config {
+ unsigned int enabled_uarts;
+ };
+
++/* Use these macros in board setup code to enable a specific UART. */
++#define DAVINCI_UART0_ENA (1 << 0)
++#define DAVINCI_UART1_ENA (1 << 1)
++#define DAVINCI_UART2_ENA (1 << 2)
++
+ extern void davinci_serial_init(struct davinci_uart_config *);
+
+ #endif /* __ASM_ARCH_SERIAL_H */
+--
+1.5.4.5
+
--- /dev/null
+From 2e852db8367da3d3f60230419bd36bab2535c0ff Mon Sep 17 00:00:00 2001
+From: Hugo Villeneuve <hugo@hugovil.com>
+Date: Thu, 5 Mar 2009 17:11:05 -0500
+Subject: [PATCH 04/12] Davinci: Enable MAC address to be specified on kernel cmd line
+
+Signed-off-by: Hugo Villeneuve <hugo@hugovil.com>
+---
+ arch/arm/mach-davinci/devices.c | 23 +++++++++++++++++++++++
+ 1 files changed, 23 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
+index a0f5a60..db433be 100644
+--- a/arch/arm/mach-davinci/devices.c
++++ b/arch/arm/mach-davinci/devices.c
+@@ -353,6 +353,27 @@ static struct platform_device dm646x_emac_device = {
+ }
+ };
+
++/* Get Ethernet address from kernel boot params */
++static u8 davinci_bootloader_mac_addr[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
++
++static int /*__init */ davinci_bootloader_mac_setup(char *str)
++{
++ int i;
++
++ if (str == NULL)
++ return 0;
++
++ /* Conversion of a MAC address from a string (AA:BB:CC:DD:EE:FF)
++ * to a 6 bytes array. */
++ for (i = 0; i < 6; i++)
++ davinci_bootloader_mac_addr[i] =
++ simple_strtol(&str[i*3], (char **)NULL, 16);
++
++ return 1;
++}
++/* Get MAC address from kernel boot parameter eth=AA:BB:CC:DD:EE:FF */
++__setup("eth=", davinci_bootloader_mac_setup);
++
+ void davinci_init_emac(char *mac_addr)
+ {
+ DECLARE_MAC_BUF(buf);
+@@ -366,6 +387,8 @@ void davinci_init_emac(char *mac_addr)
+
+ if (mac_addr && is_valid_ether_addr(mac_addr))
+ memcpy(emac_pdata.mac_addr, mac_addr, 6);
++ else if (is_valid_ether_addr(davinci_bootloader_mac_addr))
++ memcpy(emac_pdata.mac_addr, davinci_bootloader_mac_addr, 6);
+ else {
+ /* Use random MAC if none passed */
+ random_ether_addr(emac_pdata.mac_addr);
+--
+1.5.4.5
+
--- /dev/null
+From 138af04718e9d80ed75bf3aeb7fb89fee2f97c12 Mon Sep 17 00:00:00 2001
+From: Hugo Villeneuve <hugo@hugovil.com>
+Date: Thu, 5 Mar 2009 14:17:52 -0500
+Subject: [PATCH 05/12] Add DAS, Mini-DAS and AFE-USB machine types
+
+Signed-off-by: Hugo Villeneuve <hugo@hugovil.com>
+---
+ arch/arm/tools/mach-types | 100 ++++++++++++++++++++++++++++++++++++++++++++-
+ 1 files changed, 98 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
+index 017ceba..f8c2e34 100644
+--- a/arch/arm/tools/mach-types
++++ b/arch/arm/tools/mach-types
+@@ -12,7 +12,7 @@
+ #
+ # http://www.arm.linux.org.uk/developer/machines/?action=new
+ #
+-# Last update: Thu Sep 25 10:10:50 2008
++# Last update: Sun Nov 30 16:39:36 2008
+ #
+ # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
+ #
+@@ -1771,7 +1771,7 @@ axs_ultrax MACH_AXS_ULTRAX AXS_ULTRAX 1779
+ at572d940deb MACH_AT572D940DEB AT572D940DEB 1780
+ davinci_da8xx_evm MACH_DAVINCI_DA8XX_EVM DAVINCI_DA8XX_EVM 1781
+ ep9302 MACH_EP9302 EP9302 1782
+-at572d940hfeb MACH_AT572D940HFEB AT572D940HFEB 1783
++at572d940hfek MACH_AT572D940HFEB AT572D940HFEB 1783
+ cybook3 MACH_CYBOOK3 CYBOOK3 1784
+ wdg002 MACH_WDG002 WDG002 1785
+ sg560adsl MACH_SG560ADSL SG560ADSL 1786
+@@ -1899,3 +1899,99 @@ rut100 MACH_RUT100 RUT100 1908
+ asusp535 MACH_ASUSP535 ASUSP535 1909
+ htcraphael MACH_HTCRAPHAEL HTCRAPHAEL 1910
+ sygdg1 MACH_SYGDG1 SYGDG1 1911
++sygdg2 MACH_SYGDG2 SYGDG2 1912
++seoul MACH_SEOUL SEOUL 1913
++salerno MACH_SALERNO SALERNO 1914
++ucn_s3c64xx MACH_UCN_S3C64XX UCN_S3C64XX 1915
++msm7201a MACH_MSM7201A MSM7201A 1916
++lpr1 MACH_LPR1 LPR1 1917
++armadillo500fx MACH_ARMADILLO500FX ARMADILLO500FX 1918
++g3evm MACH_G3EVM G3EVM 1919
++z3_dm355 MACH_Z3_DM355 Z3_DM355 1920
++w90p910evb MACH_W90P910EVB W90P910EVB 1921
++w90p920evb MACH_W90P920EVB W90P920EVB 1922
++w90p950evb MACH_W90P950EVB W90P950EVB 1923
++w90n960evb MACH_W90N960EVB W90N960EVB 1924
++camhd MACH_CAMHD CAMHD 1925
++mvc100 MACH_MVC100 MVC100 1926
++electrum_200 MACH_ELECTRUM_200 ELECTRUM_200 1927
++htcjade MACH_HTCJADE HTCJADE 1928
++memphis MACH_MEMPHIS MEMPHIS 1929
++imx27sbc MACH_IMX27SBC IMX27SBC 1930
++lextar MACH_LEXTAR LEXTAR 1931
++mv88f6281gtw_ge MACH_MV88F6281GTW_GE MV88F6281GTW_GE 1932
++ncp MACH_NCP NCP 1933
++z32an_series MACH_Z32AN Z32AN 1934
++tmq_capd MACH_TMQ_CAPD TMQ_CAPD 1935
++omap3_wl MACH_OMAP3_WL OMAP3_WL 1936
++chumby MACH_CHUMBY CHUMBY 1937
++atsarm9 MACH_ATSARM9 ATSARM9 1938
++davinci_dm365_evm MACH_DAVINCI_DM365_EVM DAVINCI_DM365_EVM 1939
++bahamas MACH_BAHAMAS BAHAMAS 1940
++das MACH_DAS DAS 1941
++minidas MACH_MINIDAS MINIDAS 1942
++vk1000 MACH_VK1000 VK1000 1943
++centro MACH_CENTRO CENTRO 1944
++ctera_2bay MACH_CTERA_2BAY CTERA_2BAY 1945
++edgeconnect MACH_EDGECONNECT EDGECONNECT 1946
++nd27000 MACH_ND27000 ND27000 1947
++cobra MACH_GEMALTO_COBRA GEMALTO_COBRA 1948
++ingelabs_comet MACH_INGELABS_COMET INGELABS_COMET 1949
++pollux_wiz MACH_POLLUX_WIZ POLLUX_WIZ 1950
++blackstone MACH_BLACKSTONE BLACKSTONE 1951
++topaz MACH_TOPAZ TOPAZ 1952
++aixle MACH_AIXLE AIXLE 1953
++mw998 MACH_MW998 MW998 1954
++nokia_rx51 MACH_NOKIA_RX51 NOKIA_RX51 1955
++vsc5605ev MACH_VSC5605EV VSC5605EV 1956
++nt98700dk MACH_NT98700DK NT98700DK 1957
++icontact MACH_ICONTACT ICONTACT 1958
++swarco_frcpu MACH_SWARCO_FRCPU SWARCO_FRCPU 1959
++swarco_scpu MACH_SWARCO_SCPU SWARCO_SCPU 1960
++bbox_p16 MACH_BBOX_P16 BBOX_P16 1961
++bstd MACH_BSTD BSTD 1962
++sbc2440ii MACH_SBC2440II SBC2440II 1963
++pcm034 MACH_PCM034 PCM034 1964
++neso MACH_NESO NESO 1965
++wlnx_9g20 MACH_WLNX_9G20 WLNX_9G20 1966
++omap_zoom2 MACH_OMAP_ZOOM2 OMAP_ZOOM2 1967
++totemnova MACH_TOTEMNOVA TOTEMNOVA 1968
++c5000 MACH_C5000 C5000 1969
++unipo_at91sam9263 MACH_UNIPO_AT91SAM9263 UNIPO_AT91SAM9263 1970
++ethernut5 MACH_ETHERNUT5 ETHERNUT5 1971
++arm11 MACH_ARM11 ARM11 1972
++cpuat9260 MACH_CPUAT9260 CPUAT9260 1973
++cpupxa255 MACH_CPUPXA255 CPUPXA255 1974
++cpuimx27 MACH_CPUIMX27 CPUIMX27 1975
++cheflux MACH_CHEFLUX CHEFLUX 1976
++eb_cpux9k2 MACH_EB_CPUX9K2 EB_CPUX9K2 1977
++opcotec MACH_OPCOTEC OPCOTEC 1978
++yt MACH_YT YT 1979
++motoq MACH_MOTOQ MOTOQ 1980
++bsb1 MACH_BSB1 BSB1 1981
++acs5k MACH_ACS5K ACS5K 1982
++milan MACH_MILAN MILAN 1983
++quartzv2 MACH_QUARTZV2 QUARTZV2 1984
++rsvp MACH_RSVP RSVP 1985
++rmp200 MACH_RMP200 RMP200 1986
++snapper_9260 MACH_SNAPPER_9260 SNAPPER_9260 1987
++dsm320 MACH_DSM320 DSM320 1988
++adsgcm MACH_ADSGCM ADSGCM 1989
++ase2_400 MACH_ASE2_400 ASE2_400 1990
++pizza MACH_PIZZA PIZZA 1991
++spot_ngpl MACH_SPOT_NGPL SPOT_NGPL 1992
++armata MACH_ARMATA ARMATA 1993
++exeda MACH_EXEDA EXEDA 1994
++mx31sf005 MACH_MX31SF005 MX31SF005 1995
++f5d8231_4_v2 MACH_F5D8231_4_V2 F5D8231_4_V2 1996
++q2440 MACH_Q2440 Q2440 1997
++qq2440 MACH_QQ2440 QQ2440 1998
++mini2440 MACH_MINI2440 MINI2440 1999
++colibri300 MACH_COLIBRI300 COLIBRI300 2000
++jades MACH_JADES JADES 2001
++spark MACH_SPARK SPARK 2002
++benzina MACH_BENZINA BENZINA 2003
++blaze MACH_BLAZE BLAZE 2004
++linkstation_ls_hgl MACH_LINKSTATION_LS_HGL LINKSTATION_LS_HGL 2005
++htcvenus MACH_HTCVENUS HTCVENUS 2006
++afeusb MACH_AFEUSB AFEUSB 2117
+--
+1.5.4.5
+
--- /dev/null
+From 590c788288e545ef74b77129bc8f747b5365f5d3 Mon Sep 17 00:00:00 2001
+From: Hugo Villeneuve <hugo@hugovil.com>
+Date: Thu, 15 Jan 2009 15:40:35 -0500
+Subject: [PATCH 06/12] ALSA: ASoC: DaVinci: Fix SFFSDR compilation error.
+
+Remove dependency on sffsdr_fpga_set_codec_fs() when the
+SFFSDR FPGA module is not selected.
+
+Signed-off-by: Hugo Villeneuve <hugo@hugovil.com>
+---
+ sound/soc/davinci/davinci-sffsdr.c | 20 +++++++++++++++++---
+ 1 files changed, 17 insertions(+), 3 deletions(-)
+
+diff --git a/sound/soc/davinci/davinci-sffsdr.c b/sound/soc/davinci/davinci-sffsdr.c
+index 1bbde3e..afb61bf 100644
+--- a/sound/soc/davinci/davinci-sffsdr.c
++++ b/sound/soc/davinci/davinci-sffsdr.c
+@@ -25,7 +25,9 @@
+ #include <asm/gpio.h>
+ #include <asm/dma.h>
+ #include <asm/mach-types.h>
++#ifdef CONFIG_SFFSDR_FPGA
+ #include <asm/plat-sffsdr/sffsdr-fpga.h>
++#endif
+
+ #include <mach/asp.h>
+ #include <mach/edma.h>
+@@ -42,6 +44,17 @@ static int sffsdr_hw_params(struct snd_pcm_substream *substream,
+ int fs;
+ int ret = 0;
+
++ /* Fsref can be 32000, 44100 or 48000. */
++ fs = params_rate(params);
++
++#ifndef CONFIG_SFFSDR_FPGA
++ /* Without the FPGA module, the Fs is fixed at 44100 Hz */
++ if (fs != 44100) {
++ pr_debug("warning: only 44.1 kHz is supported without SFFSDR FPGA module\n");
++ return -EINVAL;
++ }
++#endif
++
+ /* Set cpu DAI configuration:
+ * CLKX and CLKR are the inputs for the Sample Rate Generator.
+ * FSX and FSR are outputs, driven by the sample Rate Generator. */
+@@ -52,12 +65,13 @@ static int sffsdr_hw_params(struct snd_pcm_substream *substream,
+ if (ret < 0)
+ return ret;
+
+- /* Fsref can be 32000, 44100 or 48000. */
+- fs = params_rate(params);
+-
+ pr_debug("sffsdr_hw_params: rate = %d Hz\n", fs);
+
++#ifndef CONFIG_SFFSDR_FPGA
++ return 0;
++#else
+ return sffsdr_fpga_set_codec_fs(fs);
++#endif
+ }
+
+ static struct snd_soc_ops sffsdr_ops = {
+--
+1.5.4.5
+
--- /dev/null
+From ca4b0f980f8b03374f48cbb4937d3ed3150c0c3e Mon Sep 17 00:00:00 2001
+From: Hugo Villeneuve <hugo@hugovil.com>
+Date: Thu, 5 Mar 2009 17:04:41 -0500
+Subject: [PATCH 07/12] ALSA: ASoC: Davinci: Fix SFFSDR FPGA module codec FS bug.
+
+This prevented the FPGA from properly configuring the codec FS when
+the SFFSDR FPGA was compiled as a module.
+
+Signed-off-by: Hugo Villeneuve <hugo@hugovil.com>
+---
+ sound/soc/davinci/davinci-sffsdr.c | 14 +++++++-------
+ 1 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/sound/soc/davinci/davinci-sffsdr.c b/sound/soc/davinci/davinci-sffsdr.c
+index afb61bf..b20e36c 100644
+--- a/sound/soc/davinci/davinci-sffsdr.c
++++ b/sound/soc/davinci/davinci-sffsdr.c
+@@ -25,10 +25,10 @@
+ #include <asm/gpio.h>
+ #include <asm/dma.h>
+ #include <asm/mach-types.h>
+-#ifdef CONFIG_SFFSDR_FPGA
+-#include <asm/plat-sffsdr/sffsdr-fpga.h>
+-#endif
+
++#if defined(CONFIG_SFFSDR_FPGA) || defined(CONFIG_SFFSDR_FPGA_MODULE)
++#include <mach/sffsdr-fpga.h>
++#endif
+ #include <mach/asp.h>
+ #include <mach/edma.h>
+
+@@ -47,7 +47,7 @@ static int sffsdr_hw_params(struct snd_pcm_substream *substream,
+ /* Fsref can be 32000, 44100 or 48000. */
+ fs = params_rate(params);
+
+-#ifndef CONFIG_SFFSDR_FPGA
++#if !defined(CONFIG_SFFSDR_FPGA) && !defined(CONFIG_SFFSDR_FPGA_MODULE)
+ /* Without the FPGA module, the Fs is fixed at 44100 Hz */
+ if (fs != 44100) {
+ pr_debug("warning: only 44.1 kHz is supported without SFFSDR FPGA module\n");
+@@ -67,10 +67,10 @@ static int sffsdr_hw_params(struct snd_pcm_substream *substream,
+
+ pr_debug("sffsdr_hw_params: rate = %d Hz\n", fs);
+
+-#ifndef CONFIG_SFFSDR_FPGA
+- return 0;
+-#else
++#if defined(CONFIG_SFFSDR_FPGA) || defined(CONFIG_SFFSDR_FPGA_MODULE)
+ return sffsdr_fpga_set_codec_fs(fs);
++#else
++ return 0;
+ #endif
+ }
+
+--
+1.5.4.5
+
--- /dev/null
+From 867883ee8c226ce2c3a43c9d815a2ad706b1c19e Mon Sep 17 00:00:00 2001
+From: Hugo Villeneuve <hugo@hugovil.com>
+Date: Thu, 5 Mar 2009 15:43:16 -0500
+Subject: [PATCH 08/12] ALSA: ASoC: Davinci: Fix incorrect machine type for SFFSDR board
+
+Signed-off-by: Hugo Villeneuve <hugo@hugovil.com>
+---
+ sound/soc/davinci/Kconfig | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/sound/soc/davinci/Kconfig b/sound/soc/davinci/Kconfig
+index 7d3a85d..411a710 100644
+--- a/sound/soc/davinci/Kconfig
++++ b/sound/soc/davinci/Kconfig
+@@ -21,7 +21,7 @@ config SND_DAVINCI_SOC_EVM
+
+ config SND_DAVINCI_SOC_SFFSDR
+ tristate "SoC Audio support for SFFSDR"
+- depends on SND_DAVINCI_SOC && MACH_DAVINCI_SFFSDR
++ depends on SND_DAVINCI_SOC && MACH_SFFSDR
+ select SND_DAVINCI_SOC_I2S
+ select SND_SOC_PCM3008
+ select SFFSDR_FPGA
+--
+1.5.4.5
+
--- /dev/null
+From 8d9e736833e9e765098353117e022b96ccc72ab1 Mon Sep 17 00:00:00 2001
+From: Kevin Hilman <khilman@deeprootsystems.com>
+Date: Fri, 13 Feb 2009 19:36:37 -0800
+Subject: [PATCH 09/12] sound: ASoC: Fix DaVinci module unload error
+
+sound: ASoC: Fix DaVinci module unload error
+
+Fix for the error when the audio module is unloaded. On unregistering
+the platform_device, platform_device_release will free the platform
+data.If platform data is static the kernel panics when it is freed.
+Instead use the platform device helper function to add data.
+
+This change has been tested on DM644x EVM, DM644x SFFSDR and DM355 EVM.
+
+Signed-off-by: Chaithrika U S <chaithrika@ti.com>
+Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
+Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Signed-off-by: Jaroslav Kysela <perex@perex.cz>
+---
+ sound/soc/davinci/davinci-evm.c | 3 ++-
+ sound/soc/davinci/davinci-sffsdr.c | 3 ++-
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
+index 9420c96..0297703 100644
+--- a/sound/soc/davinci/davinci-evm.c
++++ b/sound/soc/davinci/davinci-evm.c
+@@ -225,7 +225,8 @@ static int __init evm_init(void)
+
+ platform_set_drvdata(evm_snd_device, &evm_snd_devdata);
+ evm_snd_devdata.dev = &evm_snd_device->dev;
+- evm_snd_device->dev.platform_data = data;
++ platform_device_add_data(evm_snd_device, &evm_snd_data,
++ sizeof(evm_snd_data));
+
+ ret = platform_device_add_resources(evm_snd_device, resources, 1);
+ if (ret) {
+diff --git a/sound/soc/davinci/davinci-sffsdr.c b/sound/soc/davinci/davinci-sffsdr.c
+index b20e36c..f3c3185 100644
+--- a/sound/soc/davinci/davinci-sffsdr.c
++++ b/sound/soc/davinci/davinci-sffsdr.c
+@@ -140,7 +140,8 @@ static int __init sffsdr_init(void)
+
+ platform_set_drvdata(sffsdr_snd_device, &sffsdr_snd_devdata);
+ sffsdr_snd_devdata.dev = &sffsdr_snd_device->dev;
+- sffsdr_snd_device->dev.platform_data = &sffsdr_snd_data;
++ platform_device_add_data(sffsdr_snd_device, &sffsdr_snd_data,
++ sizeof(sffsdr_snd_data));
+
+ ret = platform_device_add_resources(sffsdr_snd_device,
+ sffsdr_snd_resources,
+--
+1.5.4.5
+
--- /dev/null
+From 500b0887632165f77f2604b07df746b4a3a16d2c Mon Sep 17 00:00:00 2001
+From: Hugo Villeneuve <hugo@hugovil.com>
+Date: Fri, 6 Mar 2009 10:23:44 -0500
+Subject: [PATCH 10/12] Add generic FPGA bitstream loader driver
+
+This driver is a generic interface for programming a
+bitstream into a FPGA. It can work with serial or
+parallel programming interfaces and support multiple
+devices and partial reconfiguration. Currently Xilinx
+XC3S and XC4V FPGAs are implemented, but other
+manufacturers like Altera could be easily added.
+
+Signed-off-by: Hugo Villeneuve <hugo@hugovil.com>
+---
+ drivers/misc/Kconfig | 31 ++
+ drivers/misc/Makefile | 3 +
+ drivers/misc/fpgadl.c | 806 +++++++++++++++++++++++++++++++++++++++++++++
+ drivers/misc/fpgadl_par.c | 258 +++++++++++++++
+ drivers/misc/fpgadl_ser.c | 244 ++++++++++++++
+ include/linux/fpgadl.h | 96 ++++++
+ 6 files changed, 1438 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/misc/fpgadl.c
+ create mode 100644 drivers/misc/fpgadl_par.c
+ create mode 100644 drivers/misc/fpgadl_ser.c
+ create mode 100644 include/linux/fpgadl.h
+
+diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
+index a11e2a0..bdc0517 100644
+--- a/drivers/misc/Kconfig
++++ b/drivers/misc/Kconfig
+@@ -510,6 +510,37 @@ config SGI_GRU_DEBUG
+ This option enables addition debugging code for the SGI GRU driver. If
+ you are unsure, say N.
+
++config FPGADL
++ tristate "FPGA bitstream loader support"
++ help
++ This option enables support for the FPGA bitstream loader.
++
++ To compile this driver as a module, choose M here: the
++ module will be called fpgadl.
++
++ If unsure, say N.
++
++config FPGADL_SER
++ tristate "FPGA serial programming driver"
++ depends on SPI_MASTER && FPGADL
++ help
++ Say Y here if your FPGA bitstream is loaded using a serial
++ interface (SPI).
++
++ To compile this driver as a module, choose M here: the
++ module will be called fpgadl_ser.
++
++config FPGADL_PAR
++ tristate "FPGA parallel programming driver"
++ depends on FPGADL
++ select BITREVERSE
++ help
++ Say Y here if your FPGA bitstream is loaded using a parallel
++ interface.
++
++ To compile this driver as a module, choose M here: the
++ module will be called fpgadl_par.
++
+ source "drivers/misc/c2port/Kconfig"
+
+ endif # MISC_DEVICES
+diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
+index 78be134..4fb6dfc 100644
+--- a/drivers/misc/Makefile
++++ b/drivers/misc/Makefile
+@@ -32,5 +32,8 @@ obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o
+ obj-$(CONFIG_KGDB_TESTS) += kgdbts.o
+ obj-$(CONFIG_SGI_XP) += sgi-xp/
+ obj-$(CONFIG_SGI_GRU) += sgi-gru/
++obj-$(CONFIG_FPGADL) += fpgadl.o
++obj-$(CONFIG_FPGADL_SER) += fpgadl_ser.o
++obj-$(CONFIG_FPGADL_PAR) += fpgadl_par.o
+ obj-$(CONFIG_HP_ILO) += hpilo.o
+ obj-$(CONFIG_C2PORT) += c2port/
+diff --git a/drivers/misc/fpgadl.c b/drivers/misc/fpgadl.c
+new file mode 100644
+index 0000000..2f03d9b
+--- /dev/null
++++ b/drivers/misc/fpgadl.c
+@@ -0,0 +1,806 @@
++/*
++ * fpgadl core driver
++ *
++ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
++ *
++ * Based on code found in book "Linux Device Drivers" by
++ * Alessandro Rubini and Jonathan Corbet, published by O'Reilly & Associates.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/miscdevice.h>
++#include <linux/string.h>
++#include <linux/err.h>
++#include <linux/fs.h>
++#include <linux/firmware.h>
++#include <linux/delay.h>
++#include <linux/fpgadl.h>
++
++#include <asm/gpio.h>
++#include <asm/uaccess.h>
++
++#define MODULE_NAME "fpgadl"
++
++/* Define this to enable verbose debug messages */
++#define FPGADL_DEBUG 1
++
++static const char fpgadl_driver_version[] = "v1.0";
++
++/* Module parameters */
++static unsigned int fpgadl_debug;
++EXPORT_SYMBOL_GPL(fpgadl_debug);
++module_param_named(debug, fpgadl_debug, int, 0644);
++
++#ifdef FPGADL_DEBUG
++#define INFOMSG(fmt, args...) \
++ do { \
++ printk(KERN_INFO "%s: "fmt"\n", MODULE_NAME, ## args); \
++ } while (0)
++#define DBGMSG(fmt, args...) \
++ do { \
++ if (fpgadl_debug > 0) \
++ printk(KERN_DEBUG "%s: "fmt"\n", \
++ MODULE_NAME, ## args); \
++ } while (0)
++#define DBGMSG_ENTER() \
++ DBGMSG("%s() enter", __func__);
++#define DBGMSG_LEAVE() \
++ DBGMSG("%s() leave", __func__);
++#else
++#define INFOMSG(fmt, args...) do {} while (0)
++#define DBGMSG(fmt, args...) do {} while (0)
++#define DBGMSG_ENTER() do {} while (0)
++#define DBGMSG_LEAVE() do {} while (0)
++#endif
++
++#define FAILMSG(fmt, args...) \
++ do { \
++ printk(KERN_ERR "%s: "fmt"\n", MODULE_NAME, ## args); \
++ } while (0)
++
++#define FPGA_WAIT_TIMEOUT 100000
++#define XFER_SIZE 100 /* Transfer size when writing bytes to
++ * device. */
++
++#define BITSTREAM_MAX_SIZE_OVERHEAD 10240
++
++#define XC3S_WORD_SIZE 2
++#define XC4V_WORD_SIZE 4
++
++#define BITSTREAM_SYNC_BYTE1 0xAA
++#define BITSTREAM_SYNC_BYTE2 0x99
++#define BITSTREAM_SYNC_BYTE3 0x55
++#define BITSTREAM_SYNC_BYTE4 0x66
++
++#define BITSTREAM_PACKET_HEADER_TYPE1 1
++#define BITSTREAM_PACKET_HEADER_TYPE2 2
++#define BITSTREAM_TYPE1_OPCODE_WRITE 2
++#define BITSTREAM_TYPE1_REG_ADDR_FDRI 2
++
++/* Structure of a TYPE1 packet. */
++struct t1_pkt_xc4v_t {
++ u32 word_count:11;
++ u32 reserved2:2;
++ u32 address:5;
++ u32 reserved1:9;
++ u32 opcode:2;
++ u32 header:3;
++};
++
++struct t1_pkt_xc3s_t {
++ u16 word_count:5;
++ u16 address:6;
++ u16 opcode:2;
++ u16 header:3; /* type */
++};
++
++/* Structure of a TYPE2 packet. */
++struct t2_pkt_xc4v_t {
++ u32 word_count:27;
++ u32 opcode:2; /* Reserved. */
++ u32 header:3;
++};
++
++struct t2_pkt_xc3s_t {
++ u16 word_count:11;
++ u16 opcode:2; /* Reserved. */
++ u16 header:3;
++};
++
++#define MAX_FPGADL_DEV 4
++
++static int fpgadl_dev_count;
++static struct fpgadl_device *fpgadl_dev_array[MAX_FPGADL_DEV];
++
++int fpgadl_is_bitstream_loaded(const char *name)
++{
++ int k;
++ struct fpgadl_device *fpgadl_dev;
++
++ DBGMSG_ENTER();
++
++ for (k = 0; k < MAX_FPGADL_DEV; k++) {
++ fpgadl_dev = fpgadl_dev_array[k];
++ if (fpgadl_dev)
++ if (strncmp(fpgadl_dev->name, name, strlen(name)) == 0)
++ return fpgadl_dev->bitstream_loaded;
++ }
++
++ FAILMSG(" Device <%s> not found", name);
++ return -ENOMEM;
++}
++EXPORT_SYMBOL(fpgadl_is_bitstream_loaded);
++
++/* Respond to hotplug events. */
++static int fpgadl_uevent(struct device *dev, struct kobj_uevent_env *env)
++{
++ DBGMSG_ENTER();
++
++ if (add_uevent_var(env, "FPGADL_BUS_VERSION=%s", fpgadl_driver_version))
++ return -ENOMEM;
++ return 0;
++};
++
++/*
++ * Toggles the CCLK line on the board-specific interface the number of times
++ * specified by <cycles>.
++ */
++static int bitstr_load_make_clock(struct fpgadl_device *fpgadl_dev,
++ int cycles)
++{
++ int retval;
++ int k;
++ u8 dummy = 0;
++
++ for (k = 0; k < cycles; k++) {
++ retval = fpgadl_dev->write_byte(fpgadl_dev, &dummy, 1);
++ if (retval < 0)
++ return retval;
++ }
++
++ return 0;
++}
++
++/* Search for bitstream sync word. */
++static int bitstr_search_sync_word(const u8 *buffer, size_t length,
++ const u8 *sync_word, ssize_t sync_word_size)
++{
++ int k;
++
++ for (k = 0; k < length; k++, buffer++) {
++ if (memcmp(buffer, sync_word, sync_word_size) == 0) {
++ DBGMSG(" Synchronization word found at offset 0x%02X",
++ k);
++ return k;
++ }
++ }
++
++ return 0;
++}
++
++static int bitstr_get_payload_size(int fpga_family, int sws,
++ const u8 *buffer, ssize_t length)
++{
++ int index = 0;
++
++ /* Find the payload size. */
++ while (index < length) {
++ switch (fpga_family) {
++ case FPGA_FAMILY_XILINX_XC4V:
++ {
++ u32 tmp = ntohl(*((u32 *) &buffer[index]));
++ struct t1_pkt_xc4v_t *t1 =
++ (struct t1_pkt_xc4v_t *) &tmp;
++
++ /* Search for type 1 packet header. */
++ if ((t1->header == BITSTREAM_PACKET_HEADER_TYPE1) &&
++ (t1->opcode == BITSTREAM_TYPE1_OPCODE_WRITE) &&
++ (t1->address == BITSTREAM_TYPE1_REG_ADDR_FDRI)) {
++ if (t1->word_count != 0)
++ return t1->word_count;
++ else {
++ struct t2_pkt_xc4v_t *t2;
++
++ tmp = ntohl(*((u32 *)
++ &buffer[index + sws]));
++ t2 = (struct t2_pkt_xc4v_t *) &tmp;
++
++ /* Search for type 2 packet header just
++ * after type1 packet. */
++ if ((t2->header ==
++ BITSTREAM_PACKET_HEADER_TYPE2))
++ return t2->word_count;
++ }
++ }
++ }
++ break;
++ case FPGA_FAMILY_XILINX_XC3S:
++ {
++ u16 tmp = ntohs(*((u16 *) &buffer[index]));
++ struct t2_pkt_xc3s_t *t2 =
++ (struct t2_pkt_xc3s_t *) &tmp;
++
++ /* Search for type 2 packet header just after
++ * type1 packet. */
++ if ((t2->header == BITSTREAM_PACKET_HEADER_TYPE2)) {
++ DBGMSG(" Type 2 packet found at offset $%02X",
++ index);
++ return ntohl(*((u32 *) &buffer[index + sws]));
++ }
++ /* Word-size aligned when sync word has been found. */
++ index += sws;
++ }
++ break;
++ }
++
++ /* Word-size aligned when sync word has been found. */
++ index += sws;
++ }
++
++ return 0; /* Not found */
++}
++
++/*
++ * Return value:
++ * 0: Error
++ * 1: Full bitstream
++ * 2: Partial bitstream
++ */
++static int bitstream_parse_header(const u8 *buffer, size_t length,
++ int fpga_family, size_t payload_full_size)
++{
++ int index = 0;
++ size_t payload_size = 0;
++ u8 sync_word[] = {
++ BITSTREAM_SYNC_BYTE1,
++ BITSTREAM_SYNC_BYTE2,
++ BITSTREAM_SYNC_BYTE3,
++ BITSTREAM_SYNC_BYTE4,
++ };
++ int sync_word_size; /* Size in bytes */
++
++ switch (fpga_family) {
++ case FPGA_FAMILY_XILINX_XC3S:
++ sync_word_size = XC3S_WORD_SIZE;
++ break;
++ case FPGA_FAMILY_XILINX_XC4V:
++ sync_word_size = XC4V_WORD_SIZE;
++ break;
++ default:
++ FAILMSG("Error, invalid FPGA family number");
++ return BITSTREAM_MODE_UNKNOWN;
++ }
++
++ /* Search for bitstream sync word. */
++ index = bitstr_search_sync_word(buffer, length,
++ sync_word, sync_word_size);
++ if (index == 0) {
++ FAILMSG("Error: Synchronization word not found");
++ return BITSTREAM_MODE_UNKNOWN;
++ }
++
++ /* Get payload size. */
++ payload_size = bitstr_get_payload_size(fpga_family, sync_word_size,
++ &buffer[index], length - index);
++ payload_size *= sync_word_size; /* Length in bytes. */
++
++ if (payload_size == 0) {
++ /* Warning only, assuming FULL bitstream. */
++ DBGMSG(" Warning: payload size not found");
++ return BITSTREAM_MODE_FULL;
++ } else {
++ DBGMSG(" Payload size: %d kb", payload_size / 1024);
++
++ /* Is it a full or a partial bitstream? */
++ if (payload_size == payload_full_size)
++ return BITSTREAM_MODE_FULL;
++ else
++ return BITSTREAM_MODE_PARTIAL;
++ }
++}
++
++/*
++ * Bitstreams supported: Full or Partial.
++ * Note: Full bitstream that supports partial bitstream must be generated with
++ * option "Persist = true" in ISE.
++ */
++static int fpgadl_bitstream_load(struct fpgadl_device *fpgadl_dev,
++ const u8 *data, size_t size)
++{
++ int k;
++ int retval;
++ int timeout_counter;
++
++ fpgadl_dev->bitstream_loaded = 0;
++
++ fpgadl_dev->bitstream_mode =
++ bitstream_parse_header(data, size,
++ fpgadl_dev->pdata->fpga_family,
++ fpgadl_dev->pdata->payload_full_size);
++ switch (fpgadl_dev->bitstream_mode) {
++ case BITSTREAM_MODE_FULL:
++ DBGMSG(" Bitstream type: FULL");
++ /* Toggle PROG_B Pin and wait 300nS before proceeding. */
++ gpio_set_value(fpgadl_dev->pdata->program_b, 0);
++ udelay(1);
++
++ /* Confirm that INIT_B is low */
++ if (gpio_get_value(fpgadl_dev->pdata->init_b) != 0) {
++ FAILMSG("Error: INIT_B not LOW when PROG is LOW");
++ return -EIO;
++ }
++
++ break;
++ case BITSTREAM_MODE_PARTIAL:
++ DBGMSG(" Bitstream type: PARTIAL");
++ break;
++ case BITSTREAM_MODE_UNKNOWN:
++ default:
++ FAILMSG(" Bitstream type: UNKNOWN");
++ return -EINVAL;
++ break;
++ }
++
++ /* For partial bitstream, PROGRAM_B is already high. */
++ retval = bitstr_load_make_clock(fpgadl_dev, 3);
++ if (retval < 0)
++ return retval;
++
++ gpio_set_value(fpgadl_dev->pdata->program_b, 1);
++
++ /* Wait for INIT_B pin to go high. */
++ timeout_counter = 0;
++ while ((gpio_get_value(fpgadl_dev->pdata->init_b) == 0) &&
++ (timeout_counter < FPGA_WAIT_TIMEOUT)) {
++ retval = bitstr_load_make_clock(fpgadl_dev, 3);
++ if (retval < 0)
++ return retval;
++
++ timeout_counter++;
++ }
++
++ if (timeout_counter == FPGA_WAIT_TIMEOUT) {
++ /* Timeout error. */
++ FAILMSG("Error: timeout while waiting for INIT_B to go HIGH");
++ return -EIO;
++ }
++
++ /* Send actual bitstream data to FPGA one byte at a time. */
++ for (k = 0; k < size; k += XFER_SIZE) {
++ retval = fpgadl_dev->write_byte(fpgadl_dev,
++ (u8 *) &data[k], XFER_SIZE);
++ if (retval < 0)
++ return retval;
++
++ if (fpgadl_dev->pdata->check_init_low) {
++ if (gpio_get_value(fpgadl_dev->pdata->init_b) == 0) {
++ /* Error if INIT_B goes low here. */
++ FAILMSG("Error: INIT_B LOW during programming");
++ return -EIO;
++ }
++ }
++ }
++
++ /* Pulse the clock line ten times at the end. */
++ retval = bitstr_load_make_clock(fpgadl_dev, 10);
++ if (retval < 0)
++ return retval;
++
++ /* FPGA DONE pin must go high. */
++ timeout_counter = 0;
++ while ((gpio_get_value(fpgadl_dev->pdata->done) == 0) &&
++ (timeout_counter < FPGA_WAIT_TIMEOUT))
++ timeout_counter++;
++
++ if (gpio_get_value(fpgadl_dev->pdata->done) == 0) {
++ /* Timeout error. */
++ FAILMSG("Error: timeout while waiting for DONE to go HIGH");
++ return -EIO;
++ }
++
++ INFOMSG("Bitstream loaded");
++ fpgadl_dev->bitstream_loaded = 1;
++
++ return 0;
++}
++
++/* Open method. */
++static int fpgadl_open(struct inode *inode, struct file *filp)
++{
++ int k;
++ int found = 0;
++ struct fpgadl_device *fpgadl_dev;
++
++ DBGMSG_ENTER();
++ DBGMSG(" Opening device minor %d", MINOR(inode->i_rdev));
++
++ for (k = 0; k < fpgadl_dev_count; k++) {
++ fpgadl_dev = fpgadl_dev_array[k];
++ if (fpgadl_dev) {
++ if (fpgadl_dev->miscdev.minor == MINOR(inode->i_rdev)) {
++ found = 1;
++ break;
++ }
++ }
++ }
++
++ if (!found) {
++ FAILMSG(" Invalid minor device");
++ return -ENOMEM;
++ }
++
++ filp->private_data = fpgadl_dev;
++
++ fpgadl_dev->bitstream_length = 0;
++ fpgadl_dev->bitstream_data = kmalloc(fpgadl_dev->bitstream_max_size,
++ GFP_KERNEL);
++ if (!fpgadl_dev->bitstream_data) {
++ FAILMSG("Failed to allocate memory for bitstream");
++ return -ENOMEM;
++ }
++
++ fpgadl_dev->bitstream_buffer_allocated = 1;
++
++ return 0;
++}
++
++/* Write method. Fill buffer with bitstream data. */
++static ssize_t fpgadl_write(struct file *filp, const char __user *buff,
++ size_t count, loff_t *offp)
++{
++ struct fpgadl_device *fpgadl_dev = filp->private_data;
++
++ if ((fpgadl_dev->bitstream_length + count) >=
++ fpgadl_dev->bitstream_max_size) {
++ FAILMSG("Bitstream buffer size exceeded");
++ return -EFBIG;
++ }
++
++ if (copy_from_user(fpgadl_dev->bitstream_data +
++ fpgadl_dev->bitstream_length,
++ (void __user *) buff, count))
++ return -EFAULT;
++
++ fpgadl_dev->bitstream_length += count;
++
++ return count;
++}
++
++/* Release method. This will initiate the FPGA programming. */
++static int fpgadl_release(struct inode *inode, struct file *filp)
++{
++ int retval;
++ struct fpgadl_device *fpgadl_dev = filp->private_data;
++
++ if (!fpgadl_dev->bitstream_data)
++ return -EFAULT;
++
++ retval = fpgadl_bitstream_load(fpgadl_dev,
++ fpgadl_dev->bitstream_data,
++ fpgadl_dev->bitstream_length);
++ kfree(fpgadl_dev->bitstream_data);
++ fpgadl_dev->bitstream_buffer_allocated = 0;
++
++ return retval;
++}
++
++static struct file_operations fops_fpgadl = {
++ .owner = THIS_MODULE,
++ .open = fpgadl_open,
++ .write = fpgadl_write,
++ .release = fpgadl_release
++};
++
++/* Match fpgadl devices to drivers. Just do a simple name test. */
++static int fpgadl_device_match(struct device *dev,
++ struct device_driver *drv)
++{
++ DBGMSG_ENTER();
++ return !strncmp(dev->bus_id, drv->name, strlen(drv->name));
++}
++
++static ssize_t show_version(struct device_driver *driver, char *buf)
++{
++ struct fpgadl_driver *fpgadldriver = to_fpgadl_driver(driver);
++
++ sprintf(buf, "%s\n", fpgadldriver->version);
++ return strlen(buf);
++}
++
++int fpgadl_register_driver(struct fpgadl_driver *drv)
++{
++ int res;
++
++ DBGMSG_ENTER();
++
++ /* Initialize common driver fields */
++ drv->driver.bus = &fpgadl_bus_type;
++
++ /* Register with core */
++ res = driver_register(&drv->driver);
++ if (res)
++ FAILMSG(" driver_register() failed");
++
++ drv->version_attr.attr.name = "version";
++ drv->version_attr.attr.owner = drv->module;
++ drv->version_attr.attr.mode = S_IRUGO;
++ drv->version_attr.show = show_version;
++ drv->version_attr.store = NULL;
++ res = driver_create_file(&drv->driver, &drv->version_attr);
++
++ return res;
++}
++EXPORT_SYMBOL(fpgadl_register_driver);
++
++void fpgadl_unregister_driver(struct fpgadl_driver *drv)
++{
++ DBGMSG_ENTER();
++ driver_unregister(&drv->driver);
++}
++EXPORT_SYMBOL(fpgadl_unregister_driver);
++
++/* The fpgadl bus device. */
++static void fpgadl_bus_release(struct device *dev)
++{
++ DBGMSG_ENTER();
++}
++
++struct device fpgadl_bus = {
++ .bus_id = "fpgadl0",
++ .release = fpgadl_bus_release
++};
++
++struct bus_type fpgadl_bus_type = {
++ .name = "fpgadl",
++ .match = fpgadl_device_match,
++ .uevent = fpgadl_uevent,
++};
++EXPORT_SYMBOL(fpgadl_bus_type);
++
++/* Export a simple sysfs attribute. */
++static ssize_t show_bus_version(struct bus_type *bus, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%s\n", fpgadl_driver_version);
++}
++
++static BUS_ATTR(version, S_IRUGO, show_bus_version, NULL);
++
++/*
++ * fpgadl devices.
++ * For now, no references to fpgadlbus devices go out which are not
++ * tracked via the module reference count, so we use a no-op
++ * release function.
++ */
++static void fpgadl_dev_release(struct device *dev)
++{
++ DBGMSG_ENTER();
++}
++
++/* Release DaVinci GPIO to FPGA control pins. */
++static void fpgadl_release_gpio(struct fpgadl_pdata_t *pdata)
++{
++ gpio_free(pdata->done);
++ gpio_free(pdata->init_b);
++ gpio_free(pdata->program_b);
++}
++
++static int fpgadl_setup_gpio(struct fpgadl_pdata_t *pdata)
++{
++ int retval;
++
++ /* Configure FPGA PROGRAM_B GPIO. */
++ retval = gpio_request(pdata->program_b, "fpga_program_b");
++ if (retval == 0) /* FPGA_PROGRAM_B must be initially HIGH. */
++ retval = gpio_direction_output(pdata->program_b, 1);
++ if (retval != 0)
++ goto gpio_error;
++
++ /* Configure FPGA INIT_B GPIO. */
++ retval = gpio_request(pdata->init_b, "fpga_init_b");
++ if (retval == 0)
++ retval = gpio_direction_input(pdata->init_b);
++ if (retval != 0)
++ goto gpio_error;
++
++ /* Configure FPGA DONE GPIO. */
++ retval = gpio_request(pdata->done, "fpga_done");
++ if (retval == 0)
++ retval = gpio_direction_input(pdata->done);
++ if (retval != 0)
++ goto gpio_error;
++
++ return 0;
++
++gpio_error:
++ fpgadl_release_gpio(pdata);
++ return retval;
++}
++
++static void fpgadl_cleanup(struct fpgadl_device *fpgadl_dev)
++{
++ DBGMSG_ENTER();
++
++ if (!fpgadl_dev)
++ return;
++
++ fpgadl_dev_array[fpgadl_dev->id] = NULL;
++
++ /* Get rid of any allocated buffer, not freed */
++ if (fpgadl_dev->bitstream_buffer_allocated)
++ kfree(fpgadl_dev->bitstream_data);
++
++ switch (fpgadl_dev->state) {
++ case FPGADL_DEV_STATE_CHAR_DEV_REGISTERED:
++ misc_deregister(&fpgadl_dev->miscdev);
++ case FPGADL_DEV_STATE_GPIO_REGISTERED:
++ fpgadl_release_gpio(fpgadl_dev->pdata);
++ case FPGADL_DEV_STATE_DEVICE_REGISTERED:
++ device_unregister(&fpgadl_dev->dev);
++ case FPGADL_DEV_STATE_START:
++ break;
++ }
++}
++
++int fpgadl_register_device(struct fpgadl_device *fpgadl_dev)
++{
++ int res;
++ const struct firmware *fw_entry;
++
++ DBGMSG_ENTER();
++
++ fpgadl_dev->state = FPGADL_DEV_STATE_START;
++
++ /* Sanity checks. */
++ if (!fpgadl_dev->name) {
++ FAILMSG(" Error, missing device name");
++ res = -EFAULT;
++ goto error;
++ }
++
++ if (!fpgadl_dev->write_byte) {
++ FAILMSG(" Error, missing write_byte() callback");
++ res = -ENOMEM;
++ goto error;
++ }
++
++ if (fpgadl_dev_count == MAX_FPGADL_DEV) {
++ FAILMSG("Maximum number of devices reached (%d)",
++ fpgadl_dev_count);
++ res = -ENODEV;
++ goto error;
++ }
++
++ DBGMSG(" device %d", fpgadl_dev_count);
++
++ /* Set some default values. */
++ fpgadl_dev->bitstream_loaded = 0;
++ fpgadl_dev->bitstream_buffer_allocated = 0;
++ fpgadl_dev->bitstream_max_size =
++ fpgadl_dev->pdata->payload_full_size +
++ BITSTREAM_MAX_SIZE_OVERHEAD;
++
++ fpgadl_dev->dev.bus = &fpgadl_bus_type;
++ fpgadl_dev->dev.parent = &fpgadl_bus;
++ fpgadl_dev->dev.release = fpgadl_dev_release;
++ strncpy(fpgadl_dev->dev.bus_id, fpgadl_dev->name, BUS_ID_SIZE);
++ res = device_register(&fpgadl_dev->dev);
++ if (res) {
++ FAILMSG(" device_register() failed");
++ goto error;
++ }
++ fpgadl_dev->state = FPGADL_DEV_STATE_DEVICE_REGISTERED;
++
++ res = fpgadl_setup_gpio(fpgadl_dev->pdata);
++ if (res < 0) {
++ FAILMSG("Error registering GPIOs");
++ goto error;
++ }
++ fpgadl_dev->state = FPGADL_DEV_STATE_GPIO_REGISTERED;
++
++ fpgadl_dev->miscdev.name = fpgadl_dev->name;
++ fpgadl_dev->miscdev.minor = MISC_DYNAMIC_MINOR;
++ fpgadl_dev->miscdev.fops = &fops_fpgadl;
++ res = misc_register(&fpgadl_dev->miscdev);
++ if (res < 0) {
++ FAILMSG("Error registering misc driver");
++ goto error;
++ }
++ DBGMSG(" MINOR = %d", fpgadl_dev->miscdev.minor);
++ fpgadl_dev->state = FPGADL_DEV_STATE_CHAR_DEV_REGISTERED;
++
++ /* Try to load firmware through hotplug if available. */
++ res = request_firmware(&fw_entry, fpgadl_dev->pdata->bitstream_name,
++ &fpgadl_dev->dev);
++ if (res < 0) {
++ /* Not an error preventing the driver from being loaded. */
++ res = 0;
++ DBGMSG("Info: firmware not available");
++ } else {
++ res = fpgadl_bitstream_load(fpgadl_dev, fw_entry->data,
++ fw_entry->size);
++ release_firmware(fw_entry);
++ }
++
++ fpgadl_dev->id = fpgadl_dev_count;
++ fpgadl_dev_array[fpgadl_dev_count] = fpgadl_dev;
++ fpgadl_dev_count++;
++
++ return 0;
++
++error:
++ fpgadl_cleanup(fpgadl_dev);
++ return res;
++}
++EXPORT_SYMBOL(fpgadl_register_device);
++
++void fpgadl_unregister_device(struct fpgadl_device *fpgadl_dev)
++{
++ DBGMSG_ENTER();
++ fpgadl_cleanup(fpgadl_dev);
++}
++EXPORT_SYMBOL(fpgadl_unregister_device);
++
++static int __init fpgadl_init(void)
++{
++ int res;
++
++ DBGMSG_ENTER();
++ INFOMSG("FPGA bitstream loader %s", fpgadl_driver_version);
++
++ res = bus_register(&fpgadl_bus_type);
++ if (res) {
++ FAILMSG(" bus_register() failed");
++ goto fail_bus;
++ }
++
++ if (bus_create_file(&fpgadl_bus_type, &bus_attr_version)) {
++ FAILMSG("Unable to create version attribute");
++ goto fail_create_file;
++ }
++
++ res = device_register(&fpgadl_bus);
++ if (res) {
++ FAILMSG(" failed registering %s", fpgadl_bus.bus_id);
++ goto fail_dev_reg;
++ }
++
++ return 0;
++
++fail_dev_reg:
++fail_create_file:
++ bus_unregister(&fpgadl_bus_type);
++fail_bus:
++ return res;
++}
++module_init(fpgadl_init);
++
++static void __exit fpgadl_exit(void)
++{
++ DBGMSG_ENTER();
++ device_unregister(&fpgadl_bus);
++ bus_unregister(&fpgadl_bus_type);
++}
++module_exit(fpgadl_exit);
++
++MODULE_AUTHOR("Hugo Villeneuve <hvilleneuve@lyrtech.com>");
++MODULE_DESCRIPTION("FPGA bitstream loader");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/misc/fpgadl_par.c b/drivers/misc/fpgadl_par.c
+new file mode 100644
+index 0000000..66f8eba
+--- /dev/null
++++ b/drivers/misc/fpgadl_par.c
+@@ -0,0 +1,258 @@
++/*
++ * fpgadl_par.c - FPGA parallel programming driver
++ *
++ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/string.h>
++#include <linux/err.h>
++#include <linux/fs.h>
++#include <linux/delay.h>
++#include <linux/bitrev.h>
++#include <linux/fpgadl.h>
++
++#include <asm/gpio.h> /* For ioremap() */
++
++#define MODULE_NAME "fpgadl_par"
++#define MODULE_VERSION_STR "v1.0"
++
++/* Define this to enable verbose debug messages */
++#define FPGADL_PAR_DEBUG 1
++
++/* Module parameters */
++static unsigned int fpgadl_par_debug;
++EXPORT_SYMBOL_GPL(fpgadl_par_debug);
++module_param_named(debug, fpgadl_par_debug, int, 0644);
++
++#ifdef FPGADL_PAR_DEBUG
++#define INFOMSG(fmt, args...) \
++do { \
++ printk(KERN_INFO "%s: "fmt"\n", MODULE_NAME, ## args); } while (0)
++#define DBGMSG(fmt, args...) \
++do { if (fpgadl_par_debug > 0) \
++ printk(KERN_DEBUG "%s: "fmt"\n", MODULE_NAME, ## args); } while (0)
++#define DBGMSG_ENTER() \
++ DBGMSG("%s() enter", __func__);
++#define DBGMSG_LEAVE() \
++ DBGMSG("%s() leave", __func__);
++#else
++#define INFOMSG(fmt, args...) do {} while (0)
++#define DBGMSG(fmt, args...) do {} while (0)
++#define DBGMSG_ENTER() do {} while (0)
++#define DBGMSG_LEAVE() do {} while (0)
++#endif
++
++#define FAILMSG(fmt, args...) \
++do { \
++ printk(KERN_ERR "%s: "fmt"\n", MODULE_NAME, ## args); } while (0)
++
++struct fpgadl_par_dev_t {
++ char devname[32];
++ enum {
++ FPGADL_PAR_DEV_STATE_STRUCT_ALLOCATED,
++ FPGADL_PAR_DEV_STATE_HAVE_IOREMAP,
++ FPGADL_PAR_DEV_STATE_FPGADL_DEV_REGISTERED,
++ } state;
++ u8 *selectmap;
++ struct fpgadl_device fpgadl_dev;
++};
++
++#define MAX_FPGADL_PAR_DEV 5
++
++static int fpgadl_par_dev_count;
++
++/*
++ * Writes a byte of data to the FPGA using the SelectMAP
++ * interface. The FPGA_SELECT_MAP_REG address is within
++ * the FPGA address space (CS3), and when we write a byte
++ * to that address, the CCLK line will be toggled.
++ */
++static int selectmap_write_byte(struct fpgadl_device *fpgadl_dev,
++ u8 *data, int size)
++{
++ int k;
++ struct fpgadl_par_dev_t *fpgadl_par_dev;
++
++ fpgadl_par_dev = (struct fpgadl_par_dev_t *) fpgadl_dev->devdata;
++
++ for (k = 0; k < size; k++)
++ fpgadl_par_dev->selectmap[0] = bitrev8(data[k]);
++
++ return 0;
++}
++
++static void fpgadl_par_cleanup(struct fpgadl_par_dev_t *dev)
++{
++ DBGMSG("fpgadl_par_cleanup");
++
++ if (!dev)
++ return;
++
++ switch (dev->state) {
++ case FPGADL_PAR_DEV_STATE_FPGADL_DEV_REGISTERED:
++ fpgadl_unregister_device(&dev->fpgadl_dev);
++ case FPGADL_PAR_DEV_STATE_HAVE_IOREMAP:
++ iounmap(dev->selectmap);
++ case FPGADL_PAR_DEV_STATE_STRUCT_ALLOCATED:
++ kfree(dev);
++ break;
++ }
++}
++
++static int __devinit fpgadl_par_probe(struct platform_device *pdev)
++{
++ int len;
++ int res;
++ struct fpgadl_par_dev_t *dev = NULL;
++ const struct resource *selectmap_res;
++
++ DBGMSG("fpgadl_par_probe()");
++
++ if (fpgadl_par_dev_count == MAX_FPGADL_PAR_DEV) {
++ FAILMSG("Maximum number of devices reached (%d)",
++ fpgadl_par_dev_count);
++ res = -ENODEV;
++ goto error;
++ }
++
++ DBGMSG(" device %d", fpgadl_par_dev_count);
++
++ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++ if (!dev) {
++ FAILMSG("Failed to allocate device structure");
++ res = -ENOMEM;
++ goto error;
++ }
++ /* Set some default values. */
++ dev->state = FPGADL_PAR_DEV_STATE_STRUCT_ALLOCATED;
++
++ if (!pdev->dev.platform_data) {
++ FAILMSG("Error getting platform data");
++ res = -ENODEV;
++ goto error;
++ }
++ dev->fpgadl_dev.pdata = pdev->dev.platform_data;
++ pdev->dev.driver_data = dev; /* Private driver data */
++
++ /* Assign virtual addresses to SELECTMAP I/O memory regions. */
++ selectmap_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
++ "selectmap");
++ if (!selectmap_res) {
++ FAILMSG("Error getting selectmap ressource");
++ res = -ENODEV;
++ goto error;
++ }
++ len = selectmap_res->end - selectmap_res->start;
++ dev->selectmap = ioremap(selectmap_res->start, len);
++ if (!dev->selectmap) {
++ FAILMSG("Can't remap selectmap register");
++ res = -ENXIO;
++ goto error;
++ }
++ dev->state = FPGADL_PAR_DEV_STATE_HAVE_IOREMAP;
++
++ dev->fpgadl_dev.write_byte = selectmap_write_byte;
++ sprintf(dev->devname, "fpgadl_par%d", fpgadl_par_dev_count);
++ DBGMSG(" NAME = %s", dev->devname);
++ dev->fpgadl_dev.name = dev->devname;
++ dev->fpgadl_dev.devdata = dev; /* For our write_byte() callback */
++ res = fpgadl_register_device(&dev->fpgadl_dev);
++ if (res < 0) {
++ FAILMSG("Error registering fpgadl_par device");
++ goto error;
++ }
++ dev->state = FPGADL_PAR_DEV_STATE_FPGADL_DEV_REGISTERED;
++
++ fpgadl_par_dev_count++;
++
++ return 0;
++
++error:
++ fpgadl_par_cleanup(dev);
++ return res;
++}
++
++static int __devexit fpgadl_par_remove(struct platform_device *pdev)
++{
++ struct fpgadl_par_dev_t *dev = platform_get_drvdata(pdev);
++
++ DBGMSG("fpgadl_par_remove()");
++
++ fpgadl_par_cleanup(dev);
++
++ return 0;
++}
++
++static struct fpgadl_driver fpgadl_par_driver = {
++ .version = MODULE_VERSION_STR,
++ .module = THIS_MODULE,
++ .driver = {
++ .name = "fpgadl_par",
++ },
++};
++
++static struct platform_driver fpgadl_platform_driver = {
++ .driver = {
++ .name = MODULE_NAME,
++ .owner = THIS_MODULE,
++ },
++ .remove = fpgadl_par_remove,
++};
++
++static int __init fpgadl_par_init(void)
++{
++ int res;
++
++ DBGMSG("fpgadl_par_init()");
++
++ /* Register with the driver core. */
++ res = fpgadl_register_driver(&fpgadl_par_driver);
++ if (res) {
++ FAILMSG("Can't register fpgadl parallel driver");
++ return res;
++ }
++
++ /* The probe function will be called for each platform device declared
++ * in board setup code. */
++ res = platform_driver_probe(&fpgadl_platform_driver,
++ fpgadl_par_probe);
++ if (res) {
++ FAILMSG("platform_driver_probe() failed");
++ return res;
++ }
++
++ return 0;
++}
++module_init(fpgadl_par_init);
++
++static void __exit fpgadl_par_exit(void)
++{
++ DBGMSG("fpgadl_par_exit()");
++ platform_driver_unregister(&fpgadl_platform_driver);
++ fpgadl_unregister_driver(&fpgadl_par_driver);
++}
++module_exit(fpgadl_par_exit);
++
++MODULE_AUTHOR("Hugo Villeneuve <hvilleneuve@lyrtech.com>");
++MODULE_DESCRIPTION("FPGA parallel programming driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/misc/fpgadl_ser.c b/drivers/misc/fpgadl_ser.c
+new file mode 100644
+index 0000000..01ca5e0
+--- /dev/null
++++ b/drivers/misc/fpgadl_ser.c
+@@ -0,0 +1,244 @@
++/*
++ * fpgadl_ser.c - FPGA serial programming driver
++ *
++ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
++ *
++ * Based on SH SCI SPI interface
++ * Copyright (c) 2008 Magnus Damm
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/spi/spi.h>
++#include <linux/fpgadl.h>
++
++#define MODULE_NAME "fpgadl_ser"
++#define MODULE_VERSION_STR "v1.0"
++
++/* Define this to enable verbose debug messages */
++#define FPGADL_SER_DEBUG 1
++
++/* Module parameters */
++static unsigned int fpgadl_ser_debug;
++EXPORT_SYMBOL_GPL(fpgadl_ser_debug);
++module_param_named(debug, fpgadl_ser_debug, int, 0644);
++
++#ifdef FPGADL_SER_DEBUG
++#define INFOMSG(fmt, args...) \
++do { \
++ printk(KERN_INFO "%s: "fmt"\n", MODULE_NAME, ## args); } while (0)
++#define DBGMSG(fmt, args...) \
++do { if (fpgadl_ser_debug > 0) \
++ printk(KERN_DEBUG "%s: "fmt"\n", MODULE_NAME, ## args); } while (0)
++#define DBGMSG_ENTER() \
++ DBGMSG("%s() enter", __func__);
++#define DBGMSG_LEAVE() \
++ DBGMSG("%s() leave", __func__);
++#else
++#define INFOMSG(fmt, args...) do {} while (0)
++#define DBGMSG(fmt, args...) do {} while (0)
++#define DBGMSG_ENTER() do {} while (0)
++#define DBGMSG_LEAVE() do {} while (0)
++#endif
++
++#define FAILMSG(fmt, args...) \
++do { \
++ printk(KERN_ERR "%s: "fmt"\n", MODULE_NAME, ## args); } while (0)
++
++struct fpgadl_ser_dev_t {
++ char devname[32];
++ enum {
++ FPGADL_SER_DEV_STATE_STRUCT_ALLOCATED,
++ FPGADL_SER_DEV_STATE_SPI_SETUP,
++ FPGADL_SER_DEV_STATE_FPGADL_DEV_REGISTERED,
++ } state;
++ struct spi_transfer t;
++ struct spi_message m;
++ struct spi_device *spi;
++ struct fpgadl_device fpgadl_dev;
++};
++
++#define MAX_FPGADL_SER_DEV 5
++
++static int fpgadl_ser_dev_count;
++
++static int fpgadl_ser_write_byte(struct fpgadl_device *fpgadl_dev,
++ u8 *data, int size)
++{
++ int status;
++ struct fpgadl_ser_dev_t *fpgadl_ser_dev;
++
++ fpgadl_ser_dev = (struct fpgadl_ser_dev_t *) fpgadl_dev->devdata;
++
++ if (!data) {
++ FAILMSG("NULL data pointer");
++ return -EFAULT;
++ }
++
++ spi_message_init(&fpgadl_ser_dev->m);
++ fpgadl_ser_dev->t.tx_buf = data;
++ fpgadl_ser_dev->t.len = size;
++ spi_message_add_tail(&fpgadl_ser_dev->t, &fpgadl_ser_dev->m);
++
++ status = spi_sync(fpgadl_ser_dev->spi, &fpgadl_ser_dev->m);
++ if (status < 0)
++ FAILMSG("spi_sync() failed (%d)", status);
++
++ return status;
++}
++
++static void fpgadl_ser_cleanup(struct fpgadl_ser_dev_t *dev)
++{
++ DBGMSG_ENTER();
++
++ if (!dev)
++ return;
++
++ switch (dev->state) {
++ case FPGADL_SER_DEV_STATE_FPGADL_DEV_REGISTERED:
++ fpgadl_unregister_device(&dev->fpgadl_dev);
++ case FPGADL_SER_DEV_STATE_SPI_SETUP:
++ case FPGADL_SER_DEV_STATE_STRUCT_ALLOCATED:
++ kfree(dev);
++ break;
++ }
++}
++
++static int __devinit fpgadl_ser_probe(struct spi_device *spi)
++{
++ int res;
++ struct fpgadl_ser_dev_t *dev = NULL;
++
++ DBGMSG_ENTER();
++
++ if (fpgadl_ser_dev_count == MAX_FPGADL_SER_DEV) {
++ FAILMSG("Maximum number of devices reached (%d)",
++ fpgadl_ser_dev_count);
++ res = -ENODEV;
++ goto error;
++ }
++
++ DBGMSG(" device %d", fpgadl_ser_dev_count);
++
++ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++ if (!dev) {
++ FAILMSG("Failed to allocate device structure");
++ res = -ENOMEM;
++ goto error;
++ }
++ /* Set some default values. */
++ dev->state = FPGADL_SER_DEV_STATE_STRUCT_ALLOCATED;
++
++ DBGMSG(" SPI mode = %d", spi->mode);
++
++ if (!spi->dev.platform_data) {
++ FAILMSG("Error getting platform data");
++ res = -ENODEV;
++ goto error;
++ }
++ dev->fpgadl_dev.pdata = spi->dev.platform_data;
++ spi->dev.driver_data = dev; /* Private driver data */
++
++ spi->bits_per_word = 8; /* Size of Tx and Rx transfers. */
++ res = spi_setup(spi);
++ if (res < 0) {
++ FAILMSG("Error setting-up SPI");
++ goto error;
++ }
++ dev->spi = spi;
++ dev->state = FPGADL_SER_DEV_STATE_SPI_SETUP;
++
++ dev->fpgadl_dev.write_byte = fpgadl_ser_write_byte;
++ sprintf(dev->devname, "fpgadl_ser%d", fpgadl_ser_dev_count);
++ DBGMSG(" NAME = %s", dev->devname);
++ dev->fpgadl_dev.name = dev->devname;
++ dev->fpgadl_dev.devdata = dev; /* For our write_byte() callback */
++ res = fpgadl_register_device(&dev->fpgadl_dev);
++ if (res < 0) {
++ FAILMSG("Error registering fpgadl_ser device");
++ goto error;
++ }
++ dev->state = FPGADL_SER_DEV_STATE_FPGADL_DEV_REGISTERED;
++
++ fpgadl_ser_dev_count++;
++
++ return 0;
++
++error:
++ fpgadl_ser_cleanup(dev);
++ return res;
++}
++
++static int __devexit fpgadl_ser_remove(struct spi_device *spi)
++{
++ struct fpgadl_ser_dev_t *dev = spi_get_drvdata(spi);
++
++ DBGMSG_ENTER();
++ fpgadl_ser_cleanup(dev);
++ return 0;
++}
++
++static struct spi_driver fpgadl_ser_spi_driver = {
++ .driver = {
++ .name = MODULE_NAME,
++ .bus = &spi_bus_type,
++ .owner = THIS_MODULE,
++ },
++ .probe = fpgadl_ser_probe,
++ .remove = fpgadl_ser_remove,
++};
++
++static struct fpgadl_driver fpgadl_ser_driver = {
++ .version = MODULE_VERSION_STR,
++ .module = THIS_MODULE,
++ .driver = {
++ .name = "fpgadl_ser",
++ },
++};
++
++static int __init fpgadl_ser_init(void)
++{
++ int res;
++
++ DBGMSG_ENTER();
++
++ /* Register with the driver core. */
++ res = fpgadl_register_driver(&fpgadl_ser_driver);
++ if (res) {
++ FAILMSG("Can't register fpgadl serial driver");
++ return res;
++ }
++
++ return spi_register_driver(&fpgadl_ser_spi_driver);
++}
++module_init(fpgadl_ser_init);
++
++static void __exit fpgadl_ser_exit(void)
++{
++ DBGMSG_ENTER();
++ spi_unregister_driver(&fpgadl_ser_spi_driver);
++ fpgadl_unregister_driver(&fpgadl_ser_driver);
++}
++module_exit(fpgadl_ser_exit);
++
++MODULE_DESCRIPTION("FPGA serial programming driver");
++MODULE_AUTHOR("Hugo Villeneuve");
++MODULE_LICENSE("GPL");
+diff --git a/include/linux/fpgadl.h b/include/linux/fpgadl.h
+new file mode 100644
+index 0000000..27d83f1
+--- /dev/null
++++ b/include/linux/fpgadl.h
+@@ -0,0 +1,96 @@
++/*
++ * FPGA bitstream load header file.
++ *
++ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#ifndef FPGADL_H
++#define FPGADL_H 1
++
++#include <linux/miscdevice.h>
++
++/* FPGA device-specific informations and functions. */
++struct fpgadl_pdata_t {
++ enum {
++ FPGA_VENDOR_XILINX,
++ FPGA_VENDOR_ALTERA,
++ } fpga_vendor;
++ enum {
++ FPGA_FAMILY_XILINX_XC3S,
++ FPGA_FAMILY_XILINX_XC4V,
++ } fpga_family;
++ ssize_t payload_full_size;
++ u8 program_b;
++ u8 init_b;
++ u8 done;
++ char *bitstream_name;
++ int check_init_low; /* Set to 1 to check that the INIT pin is low during
++ * programming. Normally, we should check if INIT_B
++ * is low during configuration, indicating a
++ * configuration error. But this may cause problems
++ * for bitstreams where the INIT_B pin is used as a
++ * GPIO after configuration. */
++};
++
++struct fpgadl_driver {
++ char *version;
++ struct module *module;
++ struct device_driver driver;
++ struct driver_attribute version_attr;
++};
++
++struct fpgadl_device {
++ int id;
++ char *name;
++ enum {
++ FPGADL_DEV_STATE_START,
++ FPGADL_DEV_STATE_DEVICE_REGISTERED,
++ FPGADL_DEV_STATE_GPIO_REGISTERED,
++ FPGADL_DEV_STATE_CHAR_DEV_REGISTERED,
++ } state;
++ int bitstream_buffer_allocated;
++ u8 *bitstream_data;
++ size_t bitstream_length;
++ size_t bitstream_max_size;
++ int bitstream_mode;
++ int bitstream_loaded;
++ int (*write_byte)(struct fpgadl_device *, u8 *, int);
++ void *devdata; /* Pointer to interface-specific (SPI/PAR) device */
++ struct miscdevice miscdev;
++ struct fpgadl_driver *driver;
++ struct fpgadl_pdata_t *pdata;
++ struct device dev;
++};
++
++/* Bitstream types. */
++#define BITSTREAM_MODE_UNKNOWN 0
++#define BITSTREAM_MODE_FULL 1
++#define BITSTREAM_MODE_PARTIAL 2
++
++extern struct bus_type fpgadl_bus_type;
++
++#define to_fpgadl_driver(drv) container_of(drv, struct fpgadl_driver, driver);
++
++extern int fpgadl_register_driver(struct fpgadl_driver *drv);
++extern void fpgadl_unregister_driver(struct fpgadl_driver *drv);
++
++extern int fpgadl_register_device(struct fpgadl_device *fpgadldev);
++extern void fpgadl_unregister_device(struct fpgadl_device *fpgadldev);
++
++int fpgadl_is_bitstream_loaded(const char *name);
++
++#endif /* FPGADL_H */
+--
+1.5.4.5
+
--- /dev/null
+From 25a91bba1bcc8d9f120e8b85b0ec53a18ccec244 Mon Sep 17 00:00:00 2001
+From: Hugo Villeneuve <hugo@hugovil.com>
+Date: Thu, 5 Mar 2009 16:04:23 -0500
+Subject: [PATCH 11/12] Add lyrvpss example driver for the SFFSDR board
+
+Currently there is only a VPFE driver in lyrvpss, and it is called luyrvpfe.
+It works with a FPGA bitstream that generates a ramp and sends it over the
+VPFE interface. The lyrvpfe driver receives an interrupt each time the HSYNC
+line is pulsed (even if the VDINT0 interrupt line is used), and stores and
+checks the data to make sure that it is valid. The driver will request a new
+frame from the FPGA each time there is a read from /proc/lyrvpfe. For example,
+to receive a new frame, issue the following:
+
+ $> cat /proc/lyrvpfe
+
+This will send a request to the FPGA (using the GPIO line) to send a new frame,
+wait one second then display the contents of the PING and PONG reception buffers.
+
+Signed-off-by: Hugo Villeneuve <hugo@hugovil.com>
+---
+ .../arm/mach-davinci/include/mach/sffsdr-lyrvpfe.h | 32 +
+ drivers/char/Kconfig | 2 +
+ drivers/char/Makefile | 2 +
+ drivers/char/lyrvpss/Kconfig | 42 ++
+ drivers/char/lyrvpss/Makefile | 8 +
+ drivers/char/lyrvpss/vpfe.c | 753 ++++++++++++++++++++
+ 6 files changed, 839 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-davinci/include/mach/sffsdr-lyrvpfe.h
+ create mode 100644 drivers/char/lyrvpss/Kconfig
+ create mode 100644 drivers/char/lyrvpss/Makefile
+ create mode 100644 drivers/char/lyrvpss/vpfe.c
+
+diff --git a/arch/arm/mach-davinci/include/mach/sffsdr-lyrvpfe.h b/arch/arm/mach-davinci/include/mach/sffsdr-lyrvpfe.h
+new file mode 100644
+index 0000000..fb47851
+--- /dev/null
++++ b/arch/arm/mach-davinci/include/mach/sffsdr-lyrvpfe.h
+@@ -0,0 +1,32 @@
++/*
++ * lyrvpfe.h
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#ifndef __LYRVPFE_H
++#define __LYRVPFE_H
++
++struct lyrvpfe_platform_data {
++ unsigned ready_gpio;
++};
++
++#endif /* __LYRVPFE_H */
+diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
+index 43d6ba8..b98a8e2 100644
+--- a/drivers/char/Kconfig
++++ b/drivers/char/Kconfig
+@@ -1073,5 +1073,7 @@ config DEVPORT
+
+ source "drivers/s390/char/Kconfig"
+
++source "drivers/char/lyrvpss/Kconfig"
++
+ endmenu
+
+diff --git a/drivers/char/Makefile b/drivers/char/Makefile
+index 438f713..8800b3f 100644
+--- a/drivers/char/Makefile
++++ b/drivers/char/Makefile
+@@ -109,6 +109,8 @@ obj-$(CONFIG_PS3_FLASH) += ps3flash.o
+ obj-$(CONFIG_JS_RTC) += js-rtc.o
+ js-rtc-y = rtc.o
+
++obj-$(CONFIG_LYRTECH_VPSS) += lyrvpss/
++
+ # Files generated that shall be removed upon make clean
+ clean-files := consolemap_deftbl.c defkeymap.c
+
+diff --git a/drivers/char/lyrvpss/Kconfig b/drivers/char/lyrvpss/Kconfig
+new file mode 100644
+index 0000000..80b1487
+--- /dev/null
++++ b/drivers/char/lyrvpss/Kconfig
+@@ -0,0 +1,42 @@
++#
++# Lyrtech VPSS drivers
++#
++
++menuconfig LYRTECH_VPSS
++ bool 'Lyrtech SFFSDR VPSS drivers'
++ depends on ARCH_DAVINCI && MACH_SFFSDR
++ help
++ This enables support for Lyrtech SFFSDR VPSS drivers.
++
++ If unsure, say N.
++
++if LYRTECH_VPSS
++
++config LYRTECH_VPFE
++ tristate "Lyrtech VPFE Driver Support"
++ help
++ This option enables support for the Lyrtech VPFE driver
++ for FPGA to DaVinci data transfers.
++
++ To compile this driver as a module, choose M here: the
++ module will be called lyrvpfe.
++
++ If unsure, say N.
++
++config LYRTECH_VPBE
++ tristate "Lyrtech VPBE Driver Support"
++ help
++ This option enables support for the Lyrtech VPBE driver
++ for DaVinci to FPGA data transfers.
++
++ To compile this driver as a module, choose M here: the
++ module will be called lyrvpbe.
++
++ If unsure, say N.
++
++config LYRVPSS_DEBUG
++ boolean "Debug support for LYRVPSSS drivers"
++ help
++ Say "yes" to enable verbose debug messaging.
++
++endif # LYRTECH_VPSS
+diff --git a/drivers/char/lyrvpss/Makefile b/drivers/char/lyrvpss/Makefile
+new file mode 100644
+index 0000000..ac36807
+--- /dev/null
++++ b/drivers/char/lyrvpss/Makefile
+@@ -0,0 +1,8 @@
++#
++# Makefile for the Lyrtech SFFSDR VPSS driver
++#
++
++obj-$(CONFIG_LYRTECH_VPFE) += lyrvpfe.o
++obj-$(CONFIG_LYRTECH_VPBE) += lyrvpbe.o
++lyrvpfe-objs := vpfe.o
++lyrvpbe-objs := vpbe.o
+diff --git a/drivers/char/lyrvpss/vpfe.c b/drivers/char/lyrvpss/vpfe.c
+new file mode 100644
+index 0000000..45e2853
+--- /dev/null
++++ b/drivers/char/lyrvpss/vpfe.c
+@@ -0,0 +1,753 @@
++/*
++ * lyrvpfe driver
++ *
++ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/string.h>
++#include <linux/delay.h>
++#include <linux/firmware.h>
++#include <linux/interrupt.h>
++#include <linux/jiffies.h>
++#include <linux/err.h>
++#include <linux/fs.h>
++#include <linux/io.h>
++#include <linux/irq.h>
++
++#ifdef CONFIG_PROC_FS
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#include <asm/uaccess.h>
++#endif /* CONFIG_PROC_FS */
++
++#include <asm/gpio.h>
++
++#include <mach/sffsdr-fpga.h>
++#include <mach/sffsdr-lyrvpfe.h>
++#include <mach/mux.h>
++#include <mach/irqs.h>
++
++#define MODULE_NAME "lyrvpfe"
++
++#ifdef CONFIG_LYRVPSS_DEBUG
++#define DBGMSG(fmt, args...) \
++ printk(KERN_INFO "%s: "fmt"\n" , MODULE_NAME, ## args)
++#else
++#define DBGMSG(fmt, args...)
++#endif
++
++#define FAILMSG(fmt, args...) \
++ printk(KERN_ERR "%s: "fmt"\n" , MODULE_NAME, ## args)
++
++#define DAVINCI_CCDC_REGS_OFFSET 0x400
++
++/* This word is written at index 0 to mark a buffer as invalid. */
++#define INVALIDATE_BUFFER_CODE 0x11222211
++
++/* Default values for our driver. */
++#define LYRVPFE_LINES_PER_FRAME 2
++#define LYRVPFE_WORDS_PER_LINE 8 /* Minimum is 8 words */
++
++/* SFFSDR VPSS limits */
++#define LYRVPFE_MAX_WORDS_PER_LINE 1024
++#define LYRVPFE_MAX_LINES_PER_FRAME 10
++#define LYRVPFE_MAX_BUFFER_SIZE 65536
++
++#define BUFFER_PING 0
++#define BUFFER_PONG 1
++
++struct ccdc_regs {
++ u32 pid;
++ u32 pcr;
++ u32 syn_mode;
++ u32 hd_vd_wid;
++ u32 pix_lines;
++ u32 horz_info;
++ u32 vert_start;
++ u32 vert_lines;
++ u32 culling;
++ u32 hsize_off;
++ u32 sdofst;
++ u32 sdr_addr;
++ u32 clamp;
++ u32 dcsub;
++ u32 colptn;
++ u32 blkcmp;
++ u32 fpc;
++ u32 fpc_addr;
++ u32 vdint;
++ u32 alaw;
++ u32 rec656if;
++ u32 ccdcfg;
++ u32 fmtcfg;
++ u32 fmt_horz;
++ u32 fmt_vert;
++ u32 unused[48];
++ u32 vp_out;
++};
++
++#define CCDC_REGS_COUNT 38
++
++#define CCDC_WEN_BIT (1 << 17)
++#define CCDC_VDHDEN_BIT (1 << 16)
++#define CCDC_VDPOL_NEG (1 << 2)
++
++/* Structure containing driver informations. */
++struct lyrvpfe_private {
++ enum {
++ LYRVPFE_INIT_START,
++ LYRVPFE_INIT_HAVE_REGS,
++ LYRVPFE_INIT_HAVE_IRQ,
++ LYRVPFE_INIT_HAVE_GPIO,
++ LYRVPFE_INIT_VPFE,
++ LYRVPFE_INIT_HAVE_PING_BUFFER,
++ LYRVPFE_INIT_HAVE_PONG_BUFFER,
++ LYRVPFE_INIT_HAVE_PROC
++ } init_state;
++ u32 id;
++ unsigned ready_gpio;
++ unsigned int irq;
++ void *regs;
++ volatile struct ccdc_regs *ccdc_regs;
++ u32 ramp_index;
++ u32 lines_per_frame;
++ u32 words_per_line;
++ int line_size;
++ int bufsize;
++ int wrid; /* 0 (ping) or 1 (pong) */
++ u32 *data_buffers[2];
++ struct device dev;
++};
++
++static struct lyrvpfe_private lyrvpfe;
++
++/* Informs the FPGA that the DaVinci can receive a new frame. */
++static void lyrvpfe_set_ready(void)
++{
++ int value;
++
++ /* Read current pin state */
++ value = gpio_get_value(lyrvpfe.ready_gpio);
++
++ /* Toggle state. */
++ value ^= 1;
++
++ /* Toggle pin. */
++ gpio_set_value(lyrvpfe.ready_gpio, value);
++}
++
++#ifdef CONFIG_PROC_FS
++
++#define LYRVPFE_PROC_NAME "lyrvpfe"
++
++static void *lyrvpfe_start(struct seq_file *m, loff_t *pos)
++{
++ return *pos < 1 ? (void *)1 : NULL;
++}
++
++static void *lyrvpfe_next(struct seq_file *m, void *v, loff_t *pos)
++{
++ ++*pos;
++ return NULL;
++}
++
++static void lyrvpfe_stop(struct seq_file *m, void *v)
++{
++}
++
++static void lyrvpfe_display_regs(char *msg, u32 *regs, int size,
++ struct seq_file *m)
++{
++ int k;
++
++ seq_printf(m, "%s:", msg);
++ for (k = 0; k < size; k++) {
++ if ((k % 4) == 0)
++ seq_printf(m, "\n");
++
++ seq_printf(m, " [$%02X] $%08X", k * 4, regs[k]);
++ }
++ seq_printf(m, "\n");
++}
++
++static int lyrvpfe_show(struct seq_file *m, void *v)
++{
++ u32 *regs;
++ unsigned long jtarget, jcurrent;
++
++ /* Toggle pin to receive next frame */
++ lyrvpfe_set_ready();
++
++ jtarget = jiffies + (1 * HZ);
++
++ /* Wait 1 second for data to arrive. */
++ do {
++ jcurrent = jiffies;
++ cpu_relax();
++ } while (time_before(jcurrent, jtarget));
++
++ regs = (u32 *) lyrvpfe.ccdc_regs;
++ lyrvpfe_display_regs("CCDC registers", regs, CCDC_REGS_COUNT, m);
++
++ seq_printf(m, "FPGA registers:\n");
++
++ seq_printf(m, " [$%04X] $%04X [$%04X] $%04X" \
++ " [$%04X] $%04X [$%04X] $%04X\n",
++ SFFSDR_FPGA_REVISION,
++ sffsdr_fpga_regread(SFFSDR_FPGA_REVISION),
++ SFFSDR_FPGA_VPSS_CONTROL,
++ sffsdr_fpga_regread(SFFSDR_FPGA_VPSS_CONTROL),
++ SFFSDR_FPGA_VPSS_TO_DSP_FIFO,
++ sffsdr_fpga_regread(SFFSDR_FPGA_VPSS_TO_DSP_FIFO),
++ SFFSDR_FPGA_VPSS_LINES_PER_FRAME,
++ sffsdr_fpga_regread(SFFSDR_FPGA_VPSS_LINES_PER_FRAME));
++
++ regs = lyrvpfe.data_buffers[BUFFER_PING];
++ lyrvpfe_display_regs("PING buffer", regs, 64, m);
++
++ regs = lyrvpfe.data_buffers[BUFFER_PONG];
++ lyrvpfe_display_regs("PONG buffer", regs, 64, m);
++
++ return 0;
++}
++
++static const struct seq_operations lyrvpfe_op = {
++ .start = lyrvpfe_start,
++ .next = lyrvpfe_next,
++ .stop = lyrvpfe_stop,
++ .show = lyrvpfe_show
++};
++
++static int lyrvpfe_open(struct inode *inode, struct file *file)
++{
++ struct seq_file *m;
++ int ret;
++
++ DBGMSG("lyrvpfe_open");
++
++ ret = seq_open(file, &lyrvpfe_op);
++ if (ret < 0)
++ return ret;
++
++ m = file->private_data;
++
++ return 0;
++}
++
++static const struct file_operations proc_lyrvpfe_operations = {
++ .open = lyrvpfe_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = seq_release,
++ .owner = THIS_MODULE,
++};
++
++static int lyrvpfe_proc_init(void)
++{
++ struct proc_dir_entry *entry;
++
++ entry = create_proc_entry(LYRVPFE_PROC_NAME, 0, NULL);
++ if (!entry) {
++ FAILMSG("Error creating proc entry");
++ return -EFAULT;
++ }
++
++ entry->proc_fops = &proc_lyrvpfe_operations;
++ entry->data = &lyrvpfe;
++
++ return 0;
++}
++
++#endif /* CONFIG_PROC_FS */
++
++static int lyrvpfe_validate_buffer(u32 *buffer)
++{
++ u8 xor, xnor;
++ u8 *cksum_data = (u8 *) buffer;
++
++ /* Compute XOR of bytes 4 and 5 */
++ xnor = ~(cksum_data[4] ^ cksum_data[5]);
++ xor = cksum_data[4] ^ cksum_data[5];
++
++ if ((xor != cksum_data[1]) || (xnor != cksum_data[0]))
++ return -1;
++ else
++ return 0;
++}
++
++static inline void lyrvpfe_invalidate_buffer(u32 *buffer)
++{
++ int line;
++ int offset;
++
++ for (line = 0; line < lyrvpfe.lines_per_frame; line++) {
++ /* Get offset of next line. */
++ offset = (line * lyrvpfe.ccdc_regs->hsize_off) / 4;
++
++ /* Mark buffer as invalid. */
++ buffer[offset] = INVALIDATE_BUFFER_CODE;
++ }
++}
++
++/*
++ * Lyrtech SFFSDR custom VPFE format:
++ *
++ * Length is in u32 units
++ *
++ * Format for each line:
++ *
++ * | u32 | bits |
++ * |offset| 31..24 | 23..16 | 15..08 | 07..00 |
++ * ============================================
++ * 0 | dummy dummy dummy dummy
++ * 1 | dummy dummy dummy dummy
++ * 2 | length length cksum cksum
++ * 3 | data0 data0 data0 data0
++ * 4 | data1 data1 data1 data1
++ * ... ...
++ */
++static int vpfe_check_buffer(u32 *buffer)
++{
++ int k;
++ int line;
++ u16 length;
++ int offset;
++ int ret;
++
++ for (line = 0; line < lyrvpfe.lines_per_frame; line++) {
++ /* Get offset of next line. */
++ offset = (line * lyrvpfe.ccdc_regs->hsize_off) / 4;
++
++ if (buffer[offset] == INVALIDATE_BUFFER_CODE) {
++ /* No error. Means that HD pulses generated the VDINT0
++ * interruption, but VD was not asserted. */
++ return -1;
++ }
++
++ /* First two words contain empty/dummy data. */
++ offset += 2;
++
++ if (line == 0) {
++ if (lyrvpfe.wrid == BUFFER_PING)
++ DBGMSG("VDINT: PING buffer");
++ else
++ DBGMSG("VDINT: PONG buffer");
++ }
++
++ ret = lyrvpfe_validate_buffer(&buffer[offset]);
++ if (ret < 0) {
++ /* This may mean a checksum error, or that
++ * the FPGA sent fewer lines than the maximum
++ * configured. */
++ FAILMSG(" Checksum error line %d", line);
++ return -1;
++ }
++
++ length = buffer[offset] >> 16;
++
++ /* Points to first data word. */
++ offset++;
++
++ for (k = 0; k < length; k++) {
++ if (buffer[offset + k] != (lyrvpfe.ramp_index + k)) {
++ FAILMSG(" Ramp error at index %d, line %d",
++ lyrvpfe.ramp_index, line);
++ FAILMSG(" read: $%08X",
++ buffer[offset + k]);
++ FAILMSG(" expected: $%08X",
++ lyrvpfe.ramp_index + k);
++
++ lyrvpfe_invalidate_buffer(buffer);
++ return -1;
++ }
++ }
++
++ lyrvpfe.ramp_index += length;
++ }
++
++ return 0;
++}
++
++static void lyrvpfe_set_ccdc_buffer(u32 *virt_address)
++{
++ lyrvpfe.ccdc_regs->sdr_addr = (u32) virt_to_phys(virt_address);
++}
++
++/*
++ * The CCDC VDINT0 and VDINT1 HD counters begin counting HD pulses from the
++ * rising edge of the external VD. The Lyrtech FPGA VPFE design only drives VD
++ * when the ARM request data by toggling the SET_VPFE_READY GPIO. Unfortunately,
++ * the FPGA never disable the HD line, and the ISR will be called all the time
++ * with invalid data when VD is not driven. This is why we need to invalidate a
++ * buffer once it has been read.
++ */
++static irqreturn_t lyrvpfe_isr(int irq, void *dev_id)
++{
++ int ret;
++ int buffer_read_id;
++
++ /* Buffer index for reading data */
++ buffer_read_id = lyrvpfe.wrid;
++
++ ret = vpfe_check_buffer(lyrvpfe.data_buffers[buffer_read_id]);
++ if (ret) {
++ /* This could mean a real error or simply that we received a
++ * dummy HD interrupt. */
++ lyrvpfe_invalidate_buffer(lyrvpfe.data_buffers[buffer_read_id]);
++ } else {
++ /* Valid data was received. We can now switch the pong-pong
++ * buffers. */
++
++ /* Switch ping-pong buffers for writing. */
++ lyrvpfe.wrid ^= 1;
++ lyrvpfe_set_ccdc_buffer(lyrvpfe.data_buffers[lyrvpfe.wrid]);
++
++ /* Make sure to invalidate the new buffer */
++ lyrvpfe_invalidate_buffer(lyrvpfe.data_buffers[lyrvpfe.wrid]);
++ }
++
++ return IRQ_HANDLED;
++}
++
++/*
++ * Configures the VPFE interface to receive data from the FPGA.
++ *
++ * lines_per_frame: Lines per frame (within the VSYNC period).
++ * words_per_line: 32-bits data words per line (within the HSYNC period).
++ */
++static int lyrvpfe_init_vpfe(u16 lines_per_frame, u16 words_per_line)
++{
++ int bytes_per_buffer;
++
++ lyrvpfe.ramp_index = 0;
++ lyrvpfe.wrid = BUFFER_PING;
++
++ if (words_per_line > LYRVPFE_MAX_WORDS_PER_LINE) {
++ FAILMSG("VPFE init: invalid words_per_line (%d)",
++ words_per_line);
++ return -1;
++ }
++
++ if (lines_per_frame > LYRVPFE_MAX_LINES_PER_FRAME) {
++ FAILMSG("VPFE init: invalid lines_per_frame (%d)",
++ lines_per_frame);
++ return -1;
++ }
++
++ bytes_per_buffer = (words_per_line + 3) * 4 * lines_per_frame;
++ if (bytes_per_buffer > LYRVPFE_MAX_BUFFER_SIZE) {
++ FAILMSG("VPFE init: wrong bytes_per_buffer (%d)",
++ bytes_per_buffer);
++ return -1;
++ }
++
++ DBGMSG(" words_per_line = $%04X", words_per_line);
++ DBGMSG(" lines_per_frame = $%04X", lines_per_frame);
++
++ /* Setup FPGA parameters */
++ sffsdr_fpga_regwrite(SFFSDR_FPGA_VPSS_TO_DSP_FIFO,
++ (words_per_line & 0x3ff) |
++ (lines_per_frame << 10));
++
++ /* 2 additional for blanking and 1 for header (length and checksum). */
++ words_per_line = words_per_line + 3;
++
++ lyrvpfe.words_per_line = words_per_line;
++ lyrvpfe.lines_per_frame = lines_per_frame;
++
++ /************************************************/
++ /* Setup Fix VPFE parameter */
++ /************************************************/
++ /* Setup VPFE Hardware */
++ lyrvpfe.ccdc_regs->syn_mode = CCDC_WEN_BIT | CCDC_VDHDEN_BIT |
++ CCDC_VDPOL_NEG;
++
++ /* Start at Line 0 */
++ lyrvpfe.ccdc_regs->vert_start = 0;
++
++ /* Disable culling */
++ lyrvpfe.ccdc_regs->culling = 0xFFFF00FF;
++
++ lyrvpfe.ccdc_regs->sdofst = 0;
++ lyrvpfe.ccdc_regs->clamp = 0;
++ lyrvpfe.ccdc_regs->dcsub = 0;
++ lyrvpfe.ccdc_regs->colptn = 0;
++ lyrvpfe.ccdc_regs->blkcmp = 0;
++ lyrvpfe.ccdc_regs->fpc = 0;
++ lyrvpfe.ccdc_regs->vdint = 0;
++ lyrvpfe.ccdc_regs->alaw = 0;
++ lyrvpfe.ccdc_regs->rec656if = 0;
++
++ /* Disable shadowing as recommended in silicon errata. Very important,
++ * if not set, a lot of problems may occur. */
++ /* VDLC: Not latched on VSYNC. */
++ lyrvpfe.ccdc_regs->ccdcfg = (1 << 15);
++
++ /************************************************/
++ /* Setup variable VPFE parameter */
++ /************************************************/
++ /* Max. length of a line */
++ lyrvpfe.ccdc_regs->horz_info = words_per_line * 4;
++
++ /* Max. number of lines per frame - 1 */
++ lyrvpfe.ccdc_regs->vert_lines = lines_per_frame - 1;
++
++ /* Offset of a line in memory (in bytes).
++ * Must be on 32 bytes boundary */
++ lyrvpfe.line_size = ((words_per_line * sizeof(u32)) + 31) & ~31;
++ lyrvpfe.ccdc_regs->hsize_off = lyrvpfe.line_size;
++
++ /* Enable CCDC */
++ lyrvpfe.ccdc_regs->pcr = 0x1;
++
++ return 0;
++}
++
++static void lyrvpfe_disable_vpfe(void)
++{
++ /* Disable CCDC */
++ lyrvpfe.ccdc_regs->pcr = 0;
++}
++
++static void lyrvpfe_dev_cleanup(void)
++{
++ DBGMSG("lyrvpfe_dev_cleanup()");
++
++ switch (lyrvpfe.init_state) {
++ case LYRVPFE_INIT_HAVE_PROC:
++#ifdef CONFIG_PROC_FS
++ remove_proc_entry(LYRVPFE_PROC_NAME, NULL);
++#endif
++ case LYRVPFE_INIT_HAVE_IRQ:
++ free_irq(lyrvpfe.irq, &lyrvpfe);
++ case LYRVPFE_INIT_HAVE_PONG_BUFFER:
++ kfree(lyrvpfe.data_buffers[BUFFER_PONG]);
++ case LYRVPFE_INIT_HAVE_PING_BUFFER:
++ kfree(lyrvpfe.data_buffers[BUFFER_PING]);
++ case LYRVPFE_INIT_VPFE:
++ lyrvpfe_disable_vpfe();
++ case LYRVPFE_INIT_HAVE_GPIO:
++ gpio_free(lyrvpfe.ready_gpio);
++ case LYRVPFE_INIT_HAVE_REGS:
++ iounmap(lyrvpfe.regs);
++ case LYRVPFE_INIT_START:
++ break;
++ }
++}
++
++struct bus_type lyrvpfe_bus_type = {
++ .name = "lyrvpfe",
++};
++EXPORT_SYMBOL(lyrvpfe_bus_type);
++
++static int lyrvpfe_probe(struct platform_device *pdev)
++{
++ struct lyrvpfe_platform_data *pdata;
++ struct resource *regs_res;
++ struct resource *irq_res;
++ int result;
++ void *buf;
++
++ DBGMSG("lyrvpfe_probe()");
++
++ /* We Should enable the VPFE with the PSC controller and PINMUX0. */
++
++ lyrvpfe.id = pdev->id;
++ lyrvpfe.dev.bus = &lyrvpfe_bus_type;
++ lyrvpfe.dev.parent = &pdev->dev;
++ snprintf(lyrvpfe.dev.bus_id, BUS_ID_SIZE, "lyrvpfe%d", lyrvpfe.id);
++ lyrvpfe.dev.bus_id[BUS_ID_SIZE - 1] = 0;
++ lyrvpfe.init_state = LYRVPFE_INIT_START;
++
++ regs_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
++ if (!regs_res) {
++ FAILMSG("Error getting REGS ressource");
++ result = -ENODEV;
++ goto error;
++ }
++
++ lyrvpfe.regs = ioremap(regs_res->start,
++ regs_res->end - regs_res->start);
++ if (!lyrvpfe.regs) {
++ FAILMSG("Can't remap CCDC registers");
++ result = -ENXIO;
++ goto error;
++ }
++ lyrvpfe.ccdc_regs = (struct ccdc_regs *)
++ (lyrvpfe.regs + DAVINCI_CCDC_REGS_OFFSET);
++
++ lyrvpfe.init_state = LYRVPFE_INIT_HAVE_REGS;
++
++ pdata = pdev->dev.platform_data;
++ if (!pdata) {
++ FAILMSG("Error getting platform data");
++ result = -ENODEV;
++ goto error;
++ }
++ lyrvpfe.dev.platform_data = pdata;
++
++ /* Configure VPFE SET READY GPIO. */
++ lyrvpfe.ready_gpio = pdata->ready_gpio;
++
++ result = gpio_request(lyrvpfe.ready_gpio, "vpfe_ready");
++ if (result == 0) {
++ /* Must start at 1, if not gives errors. */
++ result = gpio_direction_output(lyrvpfe.ready_gpio, 1);
++ }
++ if (result != 0)
++ goto error;
++
++ lyrvpfe.init_state = LYRVPFE_INIT_HAVE_GPIO;
++
++ result = lyrvpfe_init_vpfe(LYRVPFE_LINES_PER_FRAME,
++ LYRVPFE_WORDS_PER_LINE);
++ if (result < 0) {
++ FAILMSG("lyrvpfe_init_vpfe() failed (%d)", result);
++ goto error;
++ }
++ lyrvpfe.init_state = LYRVPFE_INIT_VPFE;
++
++ /* Adding 256 to compensate for 256 bytes alignment */
++ lyrvpfe.bufsize = lyrvpfe.line_size * lyrvpfe.lines_per_frame + 256;
++
++ buf = kmalloc(lyrvpfe.bufsize /*LYRVPFE_BUFFER_SIZE*/, GFP_KERNEL);
++ if (!buf) {
++ result = -ENOMEM;
++ goto error;
++ }
++ /* Buffer must be 32 bytes aligned for the hardware but must be
++ * 256 bytes aligned to cope with cache line size. */
++ lyrvpfe.data_buffers[BUFFER_PING] =
++ (u32 *) (((u32) buf + 255) & 0xFFFFFF00);
++ lyrvpfe.data_buffers[BUFFER_PING][0] = 0x11111111;
++ lyrvpfe.data_buffers[BUFFER_PING][1] = 0x22222222;
++ lyrvpfe_invalidate_buffer(lyrvpfe.data_buffers[BUFFER_PING]);
++ lyrvpfe.init_state = LYRVPFE_INIT_HAVE_PING_BUFFER;
++
++ buf = kmalloc(lyrvpfe.bufsize /*LYRVPFE_BUFFER_SIZE*/, GFP_KERNEL);
++ if (!buf) {
++ result = -ENOMEM;
++ goto error;
++ }
++ /* Buffer must be 32 bytes aligned for the hardware but must be
++ * 256 bytes aligned to cope with cache line size. */
++ lyrvpfe.data_buffers[BUFFER_PONG] =
++ (u32 *) (((u32) buf + 255) & 0xFFFFFF00);
++ lyrvpfe.data_buffers[BUFFER_PONG][0] = 0x33333333;
++ lyrvpfe.data_buffers[BUFFER_PONG][1] = 0x44444444;
++ lyrvpfe_invalidate_buffer(lyrvpfe.data_buffers[BUFFER_PONG]);
++ lyrvpfe.init_state = LYRVPFE_INIT_HAVE_PONG_BUFFER;
++
++ lyrvpfe_set_ccdc_buffer(lyrvpfe.data_buffers[lyrvpfe.wrid]);
++
++ /* setup interrupt handling */
++ irq_res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq");
++ if (!irq_res) {
++ FAILMSG("Error getting IRQ ressource");
++ result = -ENODEV;
++ goto error;
++ }
++
++ lyrvpfe.irq = irq_res->start;
++ result = request_irq(lyrvpfe.irq, lyrvpfe_isr,
++ IRQF_SHARED /*IRQF_DISABLED*/,
++ MODULE_NAME, &lyrvpfe);
++ if (result) {
++ FAILMSG("Error requesting IRQ ressource");
++ result = -ENODEV; /* To check */
++ goto error;
++ }
++
++ lyrvpfe.init_state = LYRVPFE_INIT_HAVE_IRQ;
++
++#ifdef CONFIG_PROC_FS
++ result = lyrvpfe_proc_init();
++ if (result < 0) {
++ FAILMSG("Error creating proc entry");
++ goto error;
++ }
++#endif
++
++ lyrvpfe.init_state = LYRVPFE_INIT_HAVE_PROC;
++
++ return 0;
++
++error:
++ lyrvpfe_dev_cleanup();
++ return result;
++}
++
++static int __devexit lyrvpfe_remove(struct platform_device *pdev)
++{
++ DBGMSG("lyrvpfe_remove()");
++
++ lyrvpfe_dev_cleanup();
++ return 0;
++}
++
++static struct platform_driver lyrvpfe_pdriver = {
++ .driver = {
++ .name = MODULE_NAME,
++ .owner = THIS_MODULE,
++ },
++ .remove = lyrvpfe_remove,
++};
++
++static int __init lyrvpfe_init(void)
++{
++ int res = 0;
++
++ DBGMSG("lyrvpfe_init()");
++
++ res = bus_register(&lyrvpfe_bus_type);
++ if (res) {
++ FAILMSG("bus_register() failed");
++ goto fail_bus;
++ }
++
++ res = platform_driver_probe(&lyrvpfe_pdriver, lyrvpfe_probe);
++ if (res) {
++ FAILMSG("platform_driver_probe() failed");
++ goto fail_platform;
++ }
++
++ return 0;
++
++fail_platform:
++ bus_unregister(&lyrvpfe_bus_type);
++fail_bus:
++ return res;
++}
++module_init(lyrvpfe_init);
++
++static void __exit lyrvpfe_exit(void)
++{
++ DBGMSG("lyrvpfe_exit()");
++
++ platform_driver_unregister(&lyrvpfe_pdriver);
++ bus_unregister(&lyrvpfe_bus_type);
++}
++module_exit(lyrvpfe_exit);
++
++MODULE_AUTHOR("Hugo Villeneuve <hvilleneuve@lyrtech.com>");
++MODULE_DESCRIPTION("Lyrtech SFFSDR VPFE driver");
++MODULE_LICENSE("GPL");
+--
+1.5.4.5
+
--- /dev/null
+From 97e062a70c0b1ccc5b3f8236966c13b7b79e7c13 Mon Sep 17 00:00:00 2001
+From: Hugo Villeneuve <hugo@hugovil.com>
+Date: Fri, 6 Mar 2009 12:31:34 -0500
+Subject: [PATCH 12/12] Update SFFSDR to support FPGA and lyrvpss drivers
+
+Signed-off-by: Hugo Villeneuve <hugo@hugovil.com>
+---
+ arch/arm/configs/davinci_sffsdr_defconfig | 157 +++++++++----
+ arch/arm/mach-davinci/Kconfig | 15 ++
+ arch/arm/mach-davinci/Makefile | 1 +
+ arch/arm/mach-davinci/board-sffsdr-fpga.c | 283 ++++++++++++++++++++++
+ arch/arm/mach-davinci/board-sffsdr.c | 195 ++++++++++++---
+ arch/arm/mach-davinci/include/mach/sffsdr-fpga.h | 54 ++++
+ 6 files changed, 628 insertions(+), 77 deletions(-)
+ create mode 100644 arch/arm/mach-davinci/board-sffsdr-fpga.c
+ create mode 100644 arch/arm/mach-davinci/include/mach/sffsdr-fpga.h
+
+diff --git a/arch/arm/configs/davinci_sffsdr_defconfig b/arch/arm/configs/davinci_sffsdr_defconfig
+index 8c17858..91c01f9 100644
+--- a/arch/arm/configs/davinci_sffsdr_defconfig
++++ b/arch/arm/configs/davinci_sffsdr_defconfig
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+ # Linux kernel version: 2.6.28-davinci1
+-# Fri Jan 16 12:33:07 2009
++# Fri Mar 6 12:29:19 2009
+ #
+ CONFIG_ARM=y
+ CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+@@ -179,15 +179,11 @@ CONFIG_ARCH_DAVINCI_DM644x=y
+ #
+ # CONFIG_MACH_DAVINCI_EVM is not set
+ CONFIG_MACH_SFFSDR=y
++CONFIG_SFFSDR_FPGA=m
+ CONFIG_DAVINCI_MUX=y
+ # CONFIG_DAVINCI_MUX_DEBUG is not set
+ # CONFIG_DAVINCI_MUX_WARNINGS is not set
+ # CONFIG_DAVINCI_RESET_CLOCKS is not set
+-CONFIG_DAVINCI_BOOT_TAG=y
+-
+-#
+-# DaVinci Options
+-#
+
+ #
+ # Processor Type
+@@ -206,7 +202,7 @@ CONFIG_CPU_CP15_MMU=y
+ #
+ # Processor Features
+ #
+-CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMB is not set
+ # CONFIG_CPU_ICACHE_DISABLE is not set
+ # CONFIG_CPU_DCACHE_DISABLE is not set
+ # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+@@ -378,7 +374,84 @@ CONFIG_EXTRA_FIRMWARE=""
+ # CONFIG_DEBUG_DEVRES is not set
+ # CONFIG_SYS_HYPERVISOR is not set
+ # CONFIG_CONNECTOR is not set
+-# CONFIG_MTD is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_REDBOOT_PARTS is not set
++# CONFIG_MTD_CMDLINE_PARTS is not set
++# CONFIG_MTD_AFS_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++# CONFIG_MTD_BLKDEVS is not set
++# CONFIG_MTD_BLOCK is not set
++# CONFIG_MTD_BLOCK_RO is not set
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_GPIO is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++CONFIG_MTD_NAND_DAVINCI=y
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
+ # CONFIG_PARPORT is not set
+ CONFIG_BLK_DEV=y
+ # CONFIG_BLK_DEV_COW_COMMON is not set
+@@ -387,7 +460,13 @@ CONFIG_BLK_DEV=y
+ # CONFIG_BLK_DEV_RAM is not set
+ # CONFIG_CDROM_PKTCDVD is not set
+ # CONFIG_ATA_OVER_ETH is not set
+-# CONFIG_MISC_DEVICES is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++CONFIG_FPGADL=m
++CONFIG_FPGADL_PAR=m
++# CONFIG_C2PORT is not set
+ CONFIG_HAVE_IDE=y
+ # CONFIG_IDE is not set
+
+@@ -499,6 +578,10 @@ CONFIG_UNIX98_PTYS=y
+ # CONFIG_R3964 is not set
+ # CONFIG_RAW_DRIVER is not set
+ # CONFIG_TCG_TPM is not set
++CONFIG_LYRTECH_VPSS=y
++CONFIG_LYRTECH_VPFE=m
++# CONFIG_LYRTECH_VPBE is not set
++CONFIG_LYRVPSS_DEBUG=y
+ CONFIG_I2C=y
+ CONFIG_I2C_BOARDINFO=y
+ CONFIG_I2C_CHARDEV=y
+@@ -628,11 +711,11 @@ CONFIG_SSB_POSSIBLE=y
+ # Display device support
+ #
+ # CONFIG_DISPLAY_SUPPORT is not set
+-CONFIG_SOUND=y
++CONFIG_SOUND=m
+ # CONFIG_SOUND_OSS_CORE is not set
+-CONFIG_SND=y
+-CONFIG_SND_TIMER=y
+-CONFIG_SND_PCM=y
++CONFIG_SND=m
++CONFIG_SND_TIMER=m
++CONFIG_SND_PCM=m
+ # CONFIG_SND_SEQUENCER is not set
+ # CONFIG_SND_MIXER_OSS is not set
+ # CONFIG_SND_PCM_OSS is not set
+@@ -643,38 +726,14 @@ CONFIG_SND_DYNAMIC_MINORS=y
+ # CONFIG_SND_DEBUG is not set
+ # CONFIG_SND_DRIVERS is not set
+ # CONFIG_SND_ARM is not set
+-CONFIG_SND_SOC=y
++CONFIG_SND_SOC=m
+ CONFIG_SND_DAVINCI_SOC=m
+-# CONFIG_SND_DAVINCI_SOC_SFFSDR is not set
++CONFIG_SND_DAVINCI_SOC_I2S=m
++CONFIG_SND_DAVINCI_SOC_SFFSDR=m
+ # CONFIG_SND_SOC_ALL_CODECS is not set
++CONFIG_SND_SOC_PCM3008=m
+ # CONFIG_SOUND_PRIME is not set
+ # CONFIG_USB_SUPPORT is not set
+-# CONFIG_USB_MUSB_HOST is not set
+-# CONFIG_USB_MUSB_PERIPHERAL is not set
+-# CONFIG_USB_MUSB_OTG is not set
+-# CONFIG_USB_GADGET_MUSB_HDRC is not set
+-# CONFIG_USB_GADGET_AT91 is not set
+-# CONFIG_USB_GADGET_ATMEL_USBA is not set
+-# CONFIG_USB_GADGET_FSL_USB2 is not set
+-# CONFIG_USB_GADGET_LH7A40X is not set
+-# CONFIG_USB_GADGET_OMAP is not set
+-# CONFIG_USB_GADGET_PXA25X is not set
+-# CONFIG_USB_GADGET_PXA27X is not set
+-# CONFIG_USB_GADGET_S3C2410 is not set
+-# CONFIG_USB_GADGET_M66592 is not set
+-# CONFIG_USB_GADGET_AMD5536UDC is not set
+-# CONFIG_USB_GADGET_FSL_QE is not set
+-# CONFIG_USB_GADGET_NET2280 is not set
+-# CONFIG_USB_GADGET_GOKU is not set
+-# CONFIG_USB_GADGET_DUMMY_HCD is not set
+-# CONFIG_USB_ZERO is not set
+-# CONFIG_USB_ETH is not set
+-# CONFIG_USB_GADGETFS is not set
+-# CONFIG_USB_FILE_STORAGE is not set
+-# CONFIG_USB_G_SERIAL is not set
+-# CONFIG_USB_MIDI_GADGET is not set
+-# CONFIG_USB_G_PRINTER is not set
+-# CONFIG_USB_CDC_COMPOSITE is not set
+ CONFIG_MMC=m
+ # CONFIG_MMC_DEBUG is not set
+ # CONFIG_MMC_UNSAFE_RESUME is not set
+@@ -766,6 +825,17 @@ CONFIG_TMPFS=y
+ # CONFIG_BEFS_FS is not set
+ # CONFIG_BFS_FS is not set
+ # CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
+ # CONFIG_CRAMFS is not set
+ # CONFIG_VXFS_FS is not set
+ # CONFIG_MINIX_FS is not set
+@@ -1020,13 +1090,16 @@ CONFIG_CRYPTO=y
+ #
+ # Library routines
+ #
++CONFIG_BITREVERSE=y
+ # CONFIG_CRC_CCITT is not set
+ # CONFIG_CRC16 is not set
+ # CONFIG_CRC_T10DIF is not set
+ # CONFIG_CRC_ITU_T is not set
+-# CONFIG_CRC32 is not set
++CONFIG_CRC32=y
+ # CONFIG_CRC7 is not set
+ # CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
+ CONFIG_PLIST=y
+ CONFIG_HAS_IOMEM=y
+ CONFIG_HAS_IOPORT=y
+diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
+index 0010f2d..769cd6c 100644
+--- a/arch/arm/mach-davinci/Kconfig
++++ b/arch/arm/mach-davinci/Kconfig
+@@ -50,6 +50,21 @@ config MACH_SFFSDR
+ Say Y here to select the Lyrtech Small Form Factor
+ Software Defined Radio (SFFSDR) board.
+
++config SFFSDR_FPGA
++ tristate "SFFSDR SX-35 FPGA support"
++ default n
++ depends on MACH_SFFSDR
++ select FPGADL
++ select FW_LOADER
++ help
++ This driver supports the SX-35 FPGA on the Lyrtech SFFSDR board.
++ The FPGA is mainly used to generate the clocks for the audio
++ codec and for transferring data to/from the other stacked boards
++ (using the EMIF or VPSS ports).
++
++ To compile this driver as a module, choose M here: the
++ module will be called sffsdr-fpga.
++
+ config DAVINCI_MUX
+ bool "DAVINCI multiplexing support"
+ depends on ARCH_DAVINCI
+diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
+index 6783681..8a7b3c2 100644
+--- a/arch/arm/mach-davinci/Makefile
++++ b/arch/arm/mach-davinci/Makefile
+@@ -19,3 +19,4 @@ obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
+ obj-$(CONFIG_MACH_DAVINCI_DM646X_EVM) += board-dm646x-evm.o
+ obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
+ obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
++obj-$(CONFIG_SFFSDR_FPGA) += board-sffsdr-fpga.o
+diff --git a/arch/arm/mach-davinci/board-sffsdr-fpga.c b/arch/arm/mach-davinci/board-sffsdr-fpga.c
+new file mode 100644
+index 0000000..b6a64dd
+--- /dev/null
++++ b/arch/arm/mach-davinci/board-sffsdr-fpga.c
+@@ -0,0 +1,283 @@
++/*
++ * SFFSDR-board specific FPGA driver
++ *
++ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/string.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/cdev.h>
++#include <linux/fs.h>
++#include <linux/fpgadl.h>
++
++#include <asm/gpio.h>
++
++#include <mach/sffsdr-fpga.h>
++
++#define MODULE_NAME "sffsdr_fpga"
++
++/* Used to determine if the bitstream is loaded. */
++#define FPGA_DEVICE_NAME "fpgadl_par0"
++
++/* Define this to have verbose debug messages. */
++#define SFFSDR_FPGA_DEBUG 1
++
++#ifdef SFFSDR_FPGA_DEBUG
++#define DBGMSG(fmt, args...) \
++ printk(KERN_INFO "%s: "fmt"\n" , MODULE_NAME, ## args)
++#define FAILMSG(fmt, args...) \
++ printk(KERN_ERR "%s: "fmt"\n" , MODULE_NAME, ## args)
++#else
++#define DBGMSG(fmt, args...)
++#define FAILMSG(fmt, args...)
++#endif
++
++#define FPGA_FULL_RESET_VAL 3
++#define FPGA_PARTIAL_RESET_VAL 2
++
++#define FPGA_DS2_ON (1<<0)
++#define FPGA_DS3_ON (1<<1)
++#define FPGA_DS4_ON (1<<2)
++#define FPGA_DS5_ON (1<<3)
++#define FPGA_DS6_ON (1<<4)
++
++/* Sampling frequency divider, bits 5:4 */
++#define FPGA_FS_DIV_BY_1 (0<<4)
++#define FPGA_FS_DIV_BY_2 (1<<4)
++#define FPGA_FS_DIV_BY_4 (2<<4)
++#define FPGA_FS_DIV_RSV (3<<4)
++
++/* Sampling rate selection, bit 2 */
++#define FPGA_SR_STANDARD (0<<2) /* Standard sampling rate, default */
++#define FPGA_SR_DOUBLE (1<<2) /* Double sampling rate */
++
++/* Sampling frequency selection, bits 1:0 */
++#define FPGA_FS_48000 (0<<0) /* 48.0 kHz (PLL 12.288 MHz) */
++#define FPGA_FS_44100 (1<<0) /* 44.1 kHz (PLL 11.2896 MHz) */
++#define FPGA_FS_32000 (2<<0) /* 32.0 kHz (PLL 8.192 MHz) */
++#define FPGA_FS_RSV (3<<0) /* Reserved */
++
++struct sffsdr_fpga_dev_t {
++ int bitstream_mode;
++ u16 *regs;
++};
++
++static enum {
++ SFFSDR_FPGA_STATE_START,
++ SFFSDR_FPGA_STATE_DRV_STRUCT_ALLOCATED,
++ SFFSDR_FPGA_STATE_REGS_MAPPED,
++} sffsdr_fpga_state;
++
++struct sffsdr_fpga_dev_t *sffsdr_fpga_dev;
++
++/* The EMIF address lines A0 to A2 are not routed to the
++ * FPGA. Therefore, the upper 16 bits are never valid. */
++u16 sffsdr_fpga_regread(int offset)
++{
++ return sffsdr_fpga_dev->regs[offset / 2];
++}
++EXPORT_SYMBOL(sffsdr_fpga_regread);
++
++void sffsdr_fpga_regwrite(int offset, u16 value)
++{
++ sffsdr_fpga_dev->regs[offset / 2] = value;
++}
++EXPORT_SYMBOL(sffsdr_fpga_regwrite);
++
++/* Reset the inside logic of the FPGA according to the
++ * bitstream mode. This is done when the bitstream has
++ * been programmed and is Lyrtech SFF-SDR specific. */
++static void sffsdr_fpga_reset(int bitstream_mode)
++{
++ u32 value;
++
++ if (bitstream_mode == BITSTREAM_MODE_FULL)
++ value = FPGA_FULL_RESET_VAL;
++ else
++ value = FPGA_PARTIAL_RESET_VAL;
++
++ sffsdr_fpga_regwrite(SFFSDR_FPGA_GLOBAL_CTRL, value);
++ sffsdr_fpga_regwrite(SFFSDR_FPGA_GLOBAL_CTRL, 0);
++}
++
++static int sffsdr_fpga_post_load(int bitstream_mode)
++{
++ DBGMSG("sffsdr_fpga_post_load()");
++
++ if (fpgadl_is_bitstream_loaded(FPGA_DEVICE_NAME) < 1) {
++ FAILMSG(" FPGA is not programmed");
++ return -ENODEV;
++ }
++
++ sffsdr_fpga_reset(bitstream_mode);
++
++ DBGMSG("FPGA Revision: %d",
++ sffsdr_fpga_regread(SFFSDR_FPGA_REVISION));
++
++ /* Light some LEDs to indicate success. */
++ sffsdr_fpga_regwrite(SFFSDR_FPGA_LED_CONTROL, FPGA_DS2_ON |
++ FPGA_DS3_ON | FPGA_DS4_ON | FPGA_DS5_ON |
++ FPGA_DS6_ON);
++
++ /* Set default CODEC clock values. */
++ sffsdr_fpga_regwrite(SFFSDR_FPGA_PLL_CODEC, FPGA_FS_DIV_BY_1 |
++ FPGA_FS_44100 | FPGA_SR_STANDARD);
++
++ return 0;
++}
++
++int sffsdr_fpga_set_codec_fs(int fs)
++{
++ u16 fs_mask;
++
++ if (fpgadl_is_bitstream_loaded(FPGA_DEVICE_NAME) < 1) {
++ FAILMSG("FPGA is not programmed");
++ return -ENODEV;
++ }
++
++ switch (fs) {
++ case 32000:
++ fs_mask = FPGA_FS_32000;
++ break;
++ case 44100:
++ fs_mask = FPGA_FS_44100;
++ break;
++ case 48000:
++ fs_mask = FPGA_FS_48000;
++ break;
++ default:
++ FAILMSG("Unsupported sampling frequency");
++ return -EFAULT;
++ break;
++ }
++
++ sffsdr_fpga_regwrite(SFFSDR_FPGA_PLL_CODEC, FPGA_FS_DIV_BY_1 |
++ fs_mask | FPGA_SR_STANDARD);
++
++ return 0;
++}
++EXPORT_SYMBOL(sffsdr_fpga_set_codec_fs);
++
++static void sffsdr_fpga_cleanup(void)
++{
++ switch (sffsdr_fpga_state) {
++ case SFFSDR_FPGA_STATE_REGS_MAPPED:
++ iounmap(sffsdr_fpga_dev->regs);
++ case SFFSDR_FPGA_STATE_DRV_STRUCT_ALLOCATED:
++ kfree(sffsdr_fpga_dev);
++ case SFFSDR_FPGA_STATE_START:
++ /* Nothing to do. */
++ break;
++ }
++}
++
++static int __devinit sffsdr_fpga_probe(struct platform_device *pdev)
++{
++ struct resource *fpgaregs_res;
++ int len;
++ int result;
++
++ DBGMSG("sffsdr_fpga_probe()");
++
++ sffsdr_fpga_state = SFFSDR_FPGA_STATE_START;
++
++ sffsdr_fpga_dev = kzalloc(sizeof(*sffsdr_fpga_dev), GFP_KERNEL);
++ if (!sffsdr_fpga_dev) {
++ FAILMSG("Failed to allocate device structure");
++ result = -ENOMEM;
++ goto error;
++ }
++ sffsdr_fpga_state = SFFSDR_FPGA_STATE_DRV_STRUCT_ALLOCATED;
++
++ pdev->dev.driver_data = sffsdr_fpga_dev; /* Private driver data */
++
++ /* Assign virtual addresses to FPGAREGS I/O memory regions. */
++ fpgaregs_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
++ "sffsdr_regs");
++ if (!fpgaregs_res) {
++ FAILMSG("Error getting fpgaregs ressource");
++ result = -ENODEV;
++ goto error;
++ }
++ len = fpgaregs_res->end - fpgaregs_res->start;
++ sffsdr_fpga_dev->regs = ioremap(fpgaregs_res->start, len);
++ if (!sffsdr_fpga_dev->regs) {
++ FAILMSG("Can't remap fpgaregs registers");
++ result = -ENXIO;
++ goto error;
++ }
++ sffsdr_fpga_state = SFFSDR_FPGA_STATE_REGS_MAPPED;
++
++ /* Temporary... */
++ sffsdr_fpga_post_load(BITSTREAM_MODE_FULL);
++
++ return 0;
++
++error:
++ sffsdr_fpga_cleanup();
++ return result;
++}
++
++static int __devexit sffsdr_fpga_remove(struct platform_device *pdev)
++{
++ DBGMSG("sffsdr_fpga_remove()");
++ sffsdr_fpga_cleanup();
++
++ return 0;
++}
++
++static struct platform_driver sffsdr_fpga_platform_driver = {
++ .driver = {
++ .name = MODULE_NAME,
++ .owner = THIS_MODULE,
++ },
++ .remove = sffsdr_fpga_remove,
++};
++
++static int __init sffsdr_fpga_init(void)
++{
++ int res;
++
++ DBGMSG("sffsdr_fpga_init()");
++
++ res = platform_driver_probe(&sffsdr_fpga_platform_driver,
++ sffsdr_fpga_probe);
++ if (res) {
++ DBGMSG("platform_driver_probe() failed");
++ return res;
++ }
++
++ return 0;
++}
++module_init(sffsdr_fpga_init);
++
++static void __exit sffsdr_fpga_exit(void)
++{
++ DBGMSG("sffsdr_fpga_exit()");
++ platform_driver_unregister(&sffsdr_fpga_platform_driver);
++}
++module_exit(sffsdr_fpga_exit);
++
++MODULE_AUTHOR("Hugo Villeneuve <hvilleneuve@lyrtech.com>");
++MODULE_DESCRIPTION("Lyrtech SFFSDR SX-35 FPGA driver");
++MODULE_LICENSE("GPL");
+diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
+index 0d83cb0..aee4472 100644
+--- a/arch/arm/mach-davinci/board-sffsdr.c
++++ b/arch/arm/mach-davinci/board-sffsdr.c
+@@ -5,8 +5,7 @@
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ *
+ * Based on DV-EVM platform, original copyright follows:
+- *
+- * Copyright (C) 2007 MontaVista Software, Inc.
++ * Copyright (C) 2007 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+@@ -29,7 +28,6 @@
+ #include <linux/dma-mapping.h>
+ #include <linux/platform_device.h>
+ #include <linux/gpio.h>
+-
+ #include <linux/i2c.h>
+ #include <linux/i2c/at24.h>
+ #include <linux/etherdevice.h>
+@@ -38,10 +36,10 @@
+ #include <linux/mtd/partitions.h>
+ #include <linux/mtd/physmap.h>
+ #include <linux/io.h>
++#include <linux/fpgadl.h>
+
+ #include <asm/setup.h>
+ #include <asm/mach-types.h>
+-
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+ #include <asm/mach/flash.h>
+@@ -51,11 +49,28 @@
+ #include <mach/emac.h>
+ #include <mach/i2c.h>
+ #include <mach/serial.h>
++#include <mach/mmc.h>
+ #include <mach/psc.h>
+ #include <mach/mux.h>
++#include <mach/nand.h>
++#include <mach/mmc.h>
++#include <mach/sffsdr-lyrvpfe.h>
++
++#define XC4VSX35_PAYLOAD_SIZE (1707240)
++
++#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
++#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
++
++#define DAVINCI_VPSS_REGS_BASE 0x01C70000
++
++#define FPGA_SELECTMAP_BASE 0x04000000
++#define FPGA_SFFSDR_REGS_BASE 0x04008000
++
++/* DDR2 memory is 256 Mbytes */
++#define DDR2_BASE 0x80000000
+
+-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
+-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
++#define SFFSDR_MMC_CD_PIN GPIO(51)
++#define SFFSDR_MMC_RO_PIN GPIO(50)
+
+ struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
+ /* U-Boot Environment: Block 0
+@@ -78,9 +93,10 @@ struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
+ },
+ };
+
+-static struct flash_platform_data davinci_sffsdr_nandflash_data = {
++static struct davinci_nand_pdata davinci_sffsdr_nandflash_data = {
+ .parts = davinci_sffsdr_nandflash_partition,
+ .nr_parts = ARRAY_SIZE(davinci_sffsdr_nandflash_partition),
++ .ecc_mode = NAND_ECC_HW,
+ };
+
+ static struct resource davinci_sffsdr_nandflash_resource[] = {
+@@ -105,9 +121,6 @@ static struct platform_device davinci_sffsdr_nandflash_device = {
+ .resource = davinci_sffsdr_nandflash_resource,
+ };
+
+-/* Get Ethernet address from kernel boot params */
+-static u8 davinci_sffsdr_mac_addr[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+-
+ static struct at24_platform_data eeprom_info = {
+ .byte_len = (64*1024) / 8,
+ .page_size = 32,
+@@ -137,12 +150,126 @@ static void __init sffsdr_init_i2c(void)
+ i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
+ }
+
++static int sffsdr_mmc_get_cd(int module)
++{
++ return gpio_get_value(SFFSDR_MMC_CD_PIN);
++}
++
++static int sffsdr_mmc_get_ro(int module)
++{
++ return gpio_get_value(SFFSDR_MMC_RO_PIN);
++}
++
++static struct davinci_mmc_config sffsdr_mmc_config = {
++ .get_cd = sffsdr_mmc_get_cd,
++ .get_ro = sffsdr_mmc_get_ro,
++ .wires = 4
++};
++
++/*
++ * The FPGA is loaded using the SelectMAP mode through
++ * the EMIF interface and some dedicated control signals:
++ *
++ * FPGA DM6446
++ * --------------------
++ * PROGRAM_B GPIO37
++ * DONE GPIO39
++ * INIT GPIO40
++ * DOUT_BUSY GPIO42 (Not used)
++ * CS_B EMIF_A13 OR CS3n
++ */
++static struct fpgadl_pdata_t fpgadl_par_pdata = {
++ .fpga_family = FPGA_FAMILY_XILINX_XC4V,
++ .payload_full_size = XC4VSX35_PAYLOAD_SIZE,
++ .program_b = GPIO(37),
++ .done = GPIO(39),
++ .init_b = GPIO(40),
++ .bitstream_name = "fpga.bit",
++ .check_init_low = 0,
++};
++
++/* FPGA physical EMIF register resources. */
++static struct resource davinci_fpgadl_par_resources[] = {
++ {
++ .name = "selectmap",
++ .start = FPGA_SELECTMAP_BASE,
++ .end = FPGA_SELECTMAP_BASE + 4 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct platform_device davinci_fpgadl_par_device = {
++ .name = "fpgadl_par", /* Name of driver */
++ .id = 0,
++ .dev = {
++ .platform_data = &fpgadl_par_pdata,
++ },
++ .num_resources = ARRAY_SIZE(davinci_fpgadl_par_resources),
++ .resource = davinci_fpgadl_par_resources,
++};
++
++/* SFFSDR specific FPGA registers. */
++static struct resource davinci_sffsdr_fpga_resources[] = {
++ {
++ .name = "sffsdr_regs",
++ .start = FPGA_SFFSDR_REGS_BASE,
++ .end = FPGA_SFFSDR_REGS_BASE + SZ_1K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct platform_device davinci_sffsdr_fpga_device = {
++ .name = "sffsdr_fpga", /* Name of driver */
++ .id = -1, /* Only one instance = -1 */
++ .num_resources = ARRAY_SIZE(davinci_sffsdr_fpga_resources),
++ .resource = davinci_sffsdr_fpga_resources,
++};
++
++static struct lyrvpfe_platform_data lyrvpfe_pdata = {
++ /*
++ * GPIO(1) for DSP to FPGA (VPBE)
++ * GPIO(0) for FPGA to DSP (VPFE)
++ */
++ .ready_gpio = GPIO(0), /* DSP to FPGA (VPFE) */
++};
++
++static struct resource lyrvpfe_resources[] = {
++ {
++ .name = "regs",
++ .start = DAVINCI_VPSS_REGS_BASE,
++ .end = DAVINCI_VPSS_REGS_BASE + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "irq",
++ .start = IRQ_VDINT0,
++ .end = IRQ_VDINT0,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device lyrvpfe_pdev = {
++ .name = "lyrvpfe",
++ .id = 0,
++ .dev = {
++ .platform_data = &lyrvpfe_pdata,
++ },
++ .resource = lyrvpfe_resources,
++ .num_resources = ARRAY_SIZE(lyrvpfe_resources),
++};
++
+ static struct platform_device *davinci_sffsdr_devices[] __initdata = {
+- &davinci_sffsdr_nandflash_device,
++ &davinci_fpgadl_par_device, /* Bitstream loading - parallel */
++ &davinci_sffsdr_fpga_device, /* Application functionality */
++ &lyrvpfe_pdev,
+ };
+
++/*
++ * UART0: console
++ * UART1: FPGA
++ */
+ static struct davinci_uart_config uart_config __initdata = {
+- .enabled_uarts = (1 << 0),
++ .enabled_uarts = DAVINCI_UART0_ENA | DAVINCI_UART1_ENA,
+ };
+
+ static void __init davinci_sffsdr_map_io(void)
+@@ -151,39 +278,37 @@ static void __init davinci_sffsdr_map_io(void)
+ dm644x_init();
+ }
+
+-static __init void davinci_sffsdr_init(void)
++static void __init davinci_sffsdr_init(void)
+ {
++ gpio_request(SFFSDR_MMC_CD_PIN, "MMC CD");
++ gpio_direction_input(SFFSDR_MMC_CD_PIN);
++ gpio_request(SFFSDR_MMC_RO_PIN, "MMC RO");
++ gpio_direction_input(SFFSDR_MMC_RO_PIN);
++
++ /* Turn UART1 MUX ON. */
++ davinci_cfg_reg(DM644X_UART1);
++
+ platform_add_devices(davinci_sffsdr_devices,
+ ARRAY_SIZE(davinci_sffsdr_devices));
+ sffsdr_init_i2c();
+- davinci_serial_init(&uart_config);
+- davinci_init_emac(davinci_sffsdr_mac_addr);
+- setup_usb(0, 0); /* We support only peripheral mode. */
+
+- /* mux VLYNQ pins */
+- davinci_cfg_reg(DM644X_VLYNQEN);
+- davinci_cfg_reg(DM644X_VLYNQWD);
+-}
++ davinci_serial_init(&uart_config);
+
+-static int davinci_cpmac_eth_setup(char *str)
+-{
+- int i;
++#if defined(CONFIG_MTD_NAND_DAVINCI) || \
++ defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
++ davinci_cfg_reg(DM644X_HPIEN_DISABLE);
++ davinci_cfg_reg(DM644X_ATAEN_DISABLE);
++ platform_device_register(&davinci_sffsdr_nandflash_device);
++#endif
+
+- if (str == NULL)
+- return 0;
++ davinci_setup_mmc(0, &sffsdr_mmc_config);
+
+- /* Conversion of a MAC address from a string (AA:BB:CC:DD:EE:FF)
+- * to a 6 bytes array. */
+- for (i = 0; i < 6; i++)
+- davinci_sffsdr_mac_addr[i] = simple_strtol(&str[i*3],
+- (char **)NULL, 16);
++ davinci_init_emac(NULL);
+
+- return 1;
++ setup_usb(0, 0); /* We support only peripheral mode. */
+ }
+-/* Get MAC address from kernel boot parameter eth=AA:BB:CC:DD:EE:FF */
+-__setup("eth=", davinci_cpmac_eth_setup);
+
+-static __init void davinci_sffsdr_irq_init(void)
++static void __init davinci_sffsdr_irq_init(void)
+ {
+ davinci_irq_init();
+ }
+@@ -195,6 +320,6 @@ MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
+ .boot_params = (DAVINCI_DDR_BASE + 0x100),
+ .map_io = davinci_sffsdr_map_io,
+ .init_irq = davinci_sffsdr_irq_init,
+- .timer = &davinci_timer,
+ .init_machine = davinci_sffsdr_init,
++ .timer = &davinci_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-davinci/include/mach/sffsdr-fpga.h b/arch/arm/mach-davinci/include/mach/sffsdr-fpga.h
+new file mode 100644
+index 0000000..6607ac0
+--- /dev/null
++++ b/arch/arm/mach-davinci/include/mach/sffsdr-fpga.h
+@@ -0,0 +1,54 @@
++/*
++ * sffsdr_fpga.h
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#ifndef __SFFSDR_FPGA_H
++#define __SFFSDR_FPGA_H
++
++#define SFFSDR_FPGA_REVISION 0x000
++#define SFFSDR_FPGA_GLOBAL_CTRL 0x040
++#define SFFSDR_FPGA_LED_CONTROL 0x300
++#define SFFSDR_FPGA_PLL_CODEC 0x800
++
++/* VPSS configuration register */
++#define SFFSDR_FPGA_VPSS_CONTROL 0xA00
++
++/* VPSS, VPBE packet size configuration register */
++#define SFFSDR_FPGA_VPSS_FROM_DSP_FIFO 0xA40
++
++/* VPSS, VPFE packet size configuration register */
++#define SFFSDR_FPGA_VPSS_TO_DSP_FIFO 0xA80
++
++/* VPSS, VPFE number of lines configuration register */
++#define SFFSDR_FPGA_VPSS_LINES_PER_FRAME 0xAC0
++
++#define SFFSDR_FPGA_CUSTOM_REG0_LSB 0xC00
++#define SFFSDR_FPGA_CUSTOM_REG0_MSB 0xC20
++
++u16 sffsdr_fpga_regread(int offset);
++
++void sffsdr_fpga_regwrite(int offset, u16 value);
++
++int sffsdr_fpga_set_codec_fs(int fs);
++
++#endif /* __SFFSDR_FPGA_H */
+--
+1.5.4.5
+
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-davinci1
+# Fri Mar 6 12:29:19 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+# CONFIG_UID16 is not set
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+# CONFIG_SHMEM is not set
+CONFIG_AIO=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+CONFIG_ARCH_DAVINCI=y
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# TI DaVinci Implementations
+#
+
+#
+# DaVinci Core Type
+#
+CONFIG_ARCH_DAVINCI_DM644x=y
+# CONFIG_ARCH_DAVINCI_DM646x is not set
+# CONFIG_ARCH_DAVINCI_DM355 is not set
+
+#
+# DaVinci Board Type
+#
+# CONFIG_MACH_DAVINCI_EVM is not set
+CONFIG_MACH_SFFSDR=y
+CONFIG_SFFSDR_FPGA=m
+CONFIG_DAVINCI_MUX=y
+# CONFIG_DAVINCI_MUX_DEBUG is not set
+# CONFIG_DAVINCI_MUX_WARNINGS is not set
+# CONFIG_DAVINCI_RESET_CLOCKS is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_BLKDEVS is not set
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_DAVINCI=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_FPGADL=m
+CONFIG_FPGADL_PAR=m
+# CONFIG_C2PORT is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+CONFIG_LXT_PHY=y
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+CONFIG_TI_DAVINCI_EMAC=y
+# CONFIG_DM9000 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_LYRTECH_VPSS=y
+CONFIG_LYRTECH_VPFE=m
+# CONFIG_LYRTECH_VPBE is not set
+CONFIG_LYRVPSS_DEBUG=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_DAVINCI=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_LP5521 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+CONFIG_SOUND=m
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_DAVINCI_SOC=m
+CONFIG_SND_DAVINCI_SOC_I2S=m
+CONFIG_SND_DAVINCI_SOC_SFFSDR=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_PCM3008=m
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=m
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_DAVINCI=m
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+++ /dev/null
-require linux-omap.inc
-
-# uncomment the below to get the latest and greatest and avoid a full reparse
-# or override in it local.conf like this: DAVINCI_SRCREV_pn-linux-davinci = "${@bb.fetch.get_srcrev(d)}"
-#DAVINCI_SRCREV = "${@bb.fetch.get_srcrev(d)}"
-DAVINCI_SRCREV ?= "f5691bc8f65a08a6cb9900a5c7099a36b2b9b7a7"
-SRCREV = "${DAVINCI_SRCREV}"
-
-DEFAULT_PREFERENCE = "-1"
-
-PV = "2.6.27+2.6.28-rc6+gitr${SRCREV}"
-
-COMPATIBLE_MACHINE = "(davinci-dvevm|davinci-sffsdr)"
-
-SRC_URI = "git://source.mvista.com/git/linux-davinci-2.6.git;protocol=git \
- file://defconfig"
-
-S = "${WORKDIR}/git"
--- /dev/null
+require linux.inc
+
+DESCRIPTION = "Linux kernel for Davinci processors"
+KERNEL_IMAGETYPE = "uImage"
+
+COMPATIBLE_MACHINE = "(davinci-dvevm|davinci-sffsdr)"
+
+DEFAULT_PREFERENCE = "-1"
+
+SRCREV = "0fc192ac07c977ad6f14333651b53096a6027bc6"
+
+PV = "2.6.27+2.6.28-rc6+gitr${SRCREV}"
+
+SRC_URI = "git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git;protocol=git \
+ file://defconfig"
+
+SRC_URI_append_davinci-sffsdr = " \
+ file://0001-USB-musb-cppi-bugfixes.patch;patch=1 \
+ file://0002-ARM-Mark-unsupported-syscalls-as-IGNORE.patch;patch=1 \
+ file://0003-Add-macros-for-enabling-a-UART.patch;patch=1 \
+ file://0004-Davinci-Enable-MAC-address-to-be-specified-on-kerne.patch;patch=1 \
+ file://0005-Add-DAS-Mini-DAS-and-AFE-USB-machine-types.patch;patch=1 \
+ file://0006-ALSA-ASoC-DaVinci-Fix-SFFSDR-compilation-error.patch;patch=1 \
+ file://0007-ALSA-ASoC-Davinci-Fix-SFFSDR-FPGA-module-codec-FS.patch;patch=1 \
+ file://0008-ALSA-ASoC-Davinci-Fix-incorrect-machine-type-for.patch;patch=1 \
+ file://0009-sound-ASoC-Fix-DaVinci-module-unload-error.patch;patch=1 \
+ file://0010-Add-generic-FPGA-bitstream-loader-driver.patch;patch=1 \
+ file://0011-Add-lyrvpss-example-driver-for-the-SFFSDR-board.patch;patch=1 \
+ file://0012-Update-SFFSDR-to-support-FPGA-and-lyrvpss-drivers.patch;patch=1 \
+ "
+
+S = "${WORKDIR}/git"
projects / vuplus_openembedded / commitdiff