1 diff -Nur u-boot-2006-04-18-1106/CREDITS u-boot-2006-04-18-1106-new/CREDITS
2 --- u-boot-2006-04-18-1106/CREDITS 2006-04-18 09:05:03.000000000 +0000
3 +++ u-boot-2006-04-18-1106-new/CREDITS 2006-07-05 11:19:44.000000000 +0000
5 E: jonathan.debruyne@siemens.atea.be
6 D: Port to Siemens IAD210 board
10 +D: initial support for Sharp Zaurus SL-C1000/3100
11 +D: initial support for Sharp Zaurus SL-C7x0/C860
12 +W: http://www.pdaXrom.org
16 D: Support for A3000 SBC board
17 diff -Nur u-boot-2006-04-18-1106/MAINTAINERS u-boot-2006-04-18-1106-new/MAINTAINERS
18 --- u-boot-2006-04-18-1106/MAINTAINERS 2006-04-18 09:05:03.000000000 +0000
19 +++ u-boot-2006-04-18-1106-new/MAINTAINERS 2006-07-05 11:19:44.000000000 +0000
22 AT91RM9200DK at91rm9200
24 +Alexander Chukov <sash@pdaXrom.org>
29 George G. Davis <gdavis@mvista.com>
32 diff -Nur u-boot-2006-04-18-1106/MAKEALL u-boot-2006-04-18-1106-new/MAKEALL
33 --- u-boot-2006-04-18-1106/MAKEALL 2006-04-18 09:05:03.000000000 +0000
34 +++ u-boot-2006-04-18-1106-new/MAKEALL 2006-07-05 11:19:44.000000000 +0000
36 adsvix cerf250 cradle csb226 \
37 delta innokom lubbock pxa255_idp \
38 wepep250 xaeniax xm250 xsengine \
40 + zylonite akita corgi \
44 diff -Nur u-boot-2006-04-18-1106/Makefile u-boot-2006-04-18-1106-new/Makefile
45 --- u-boot-2006-04-18-1106/Makefile 2006-04-18 09:05:03.000000000 +0000
46 +++ u-boot-2006-04-18-1106-new/Makefile 2006-07-05 11:19:44.000000000 +0000
48 CROSS_COMPILE = powerpc-linux-
51 -CROSS_COMPILE = arm-linux-
52 +CROSS_COMPILE = armv5tel-linux-
55 ifeq ($(HOSTARCH),i386)
56 @@ -1709,6 +1709,12 @@
58 @./mkconfig $(@:_config=) arm pxa zylonite
60 +akita_config : unconfig
61 + @./mkconfig $(@:_config=) arm pxa akita
63 +corgi_config : unconfig
64 + @./mkconfig $(@:_config=) arm pxa corgi
66 #########################################################################
68 #########################################################################
69 diff -Nur u-boot-2006-04-18-1106/README u-boot-2006-04-18-1106-new/README
70 --- u-boot-2006-04-18-1106/README 2006-04-18 09:05:03.000000000 +0000
71 +++ u-boot-2006-04-18-1106-new/README 2006-07-05 11:19:44.000000000 +0000
73 CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400,
74 CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4,
75 CONFIG_SHANNON, CONFIG_P2_OMAP730, CONFIG_SMDK2400,
76 - CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9
77 + CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9,
78 + CONFIG_AKITA, CONFIG_CORGI
80 MicroBlaze based boards:
81 ------------------------
82 diff -Nur u-boot-2006-04-18-1106/board/akita/Makefile u-boot-2006-04-18-1106-new/board/akita/Makefile
83 --- u-boot-2006-04-18-1106/board/akita/Makefile 1970-01-01 00:00:00.000000000 +0000
84 +++ u-boot-2006-04-18-1106-new/board/akita/Makefile 2006-07-05 11:19:44.000000000 +0000
87 +# board/akita/Makefile
89 +# (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
92 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
94 +# See file CREDITS for list of people who contributed to this
97 +# This program is free software; you can redistribute it and/or
98 +# modify it under the terms of the GNU General Public License as
99 +# published by the Free Software Foundation; either version 2 of
100 +# the License, or (at your option) any later version.
102 +# This program is distributed in the hope that it will be useful,
103 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
104 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
105 +# GNU General Public License for more details.
107 +# You should have received a copy of the GNU General Public License
108 +# along with this program; if not, write to the Free Software
109 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
113 +include $(TOPDIR)/config.mk
117 +OBJS := akita.o nand.o kbd.o
118 +SOBJS := lowlevel_init.o
120 +$(LIB): $(OBJS) $(SOBJS)
121 + $(AR) crv $@ $(OBJS) $(SOBJS)
124 + rm -f $(SOBJS) $(OBJS)
127 + rm -f $(LIB) core *.bak .depend
129 +#########################################################################
131 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
132 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
136 +#########################################################################
137 diff -Nur u-boot-2006-04-18-1106/board/akita/akita.c u-boot-2006-04-18-1106-new/board/akita/akita.c
138 --- u-boot-2006-04-18-1106/board/akita/akita.c 1970-01-01 00:00:00.000000000 +0000
139 +++ u-boot-2006-04-18-1106-new/board/akita/akita.c 2006-07-05 11:19:44.000000000 +0000
142 + * board/akita/akita.c
144 + * Configuration settings for the Sharp Zaurus SL-Cxx00.
146 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
148 + * portions from adsvix board configuration:
149 + * (C) Copyright 2004
150 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
151 + * (C) Copyright 2002
152 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
153 + * (C) Copyright 2002
154 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
155 + * Marius Groeger <mgroeger@sysgo.de>
157 + * See file CREDITS for list of people who contributed to this
160 + * This program is free software; you can redistribute it and/or
161 + * modify it under the terms of the GNU General Public License as
162 + * published by the Free Software Foundation; either version 2 of
163 + * the License, or (at your option) any later version.
165 + * This program is distributed in the hope that it will be useful,
166 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
167 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
168 + * GNU General Public License for more details.
170 + * You should have received a copy of the GNU General Public License
171 + * along with this program; if not, write to the Free Software
172 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
173 + * MA 02111-1307 USA
178 +void set_turbo_mode(void);
180 +/* ------------------------------------------------------------------------- */
183 + * Miscellaneous platform dependent initialisations
186 +int board_init (void)
188 + DECLARE_GLOBAL_DATA_PTR;
190 + /* memory and cpu-speed are setup before relocation */
191 + /* so we do _nothing_ here */
193 + /* arch number of Sharp Zaurus Akita : MACH_TYPE_AKITA */
194 + gd->bd->bi_arch_number = 744;
196 + /* adress of boot parameters */
197 + gd->bd->bi_boot_params = 0xa0000100;
199 + /* set cpu turbo mode */
207 +int board_late_init(void)
209 + setenv("stdout", "serial");
210 + setenv("stderr", "serial");
215 +int dram_init (void)
217 + DECLARE_GLOBAL_DATA_PTR;
219 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
220 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
221 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
222 + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
223 + gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
224 + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
225 + gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
226 + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
230 diff -Nur u-boot-2006-04-18-1106/board/akita/config.mk u-boot-2006-04-18-1106-new/board/akita/config.mk
231 --- u-boot-2006-04-18-1106/board/akita/config.mk 1970-01-01 00:00:00.000000000 +0000
232 +++ u-boot-2006-04-18-1106-new/board/akita/config.mk 2006-07-05 11:19:44.000000000 +0000
234 +TEXT_BASE = 0xa3000000
235 diff -Nur u-boot-2006-04-18-1106/board/akita/kbd.c u-boot-2006-04-18-1106-new/board/akita/kbd.c
236 --- u-boot-2006-04-18-1106/board/akita/kbd.c 1970-01-01 00:00:00.000000000 +0000
237 +++ u-boot-2006-04-18-1106-new/board/akita/kbd.c 2006-07-05 11:19:44.000000000 +0000
240 + * board/akita/kbd.c
242 + * Keyboard driver for the Sharp Zaurus SL-Cxx00.
244 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
248 + * linux/drivers/input/keyboard/spitzkbd.c
250 + * Keyboard driver for Sharp Spitz, Borzoi and Akita (SL-Cxx00 series)
252 + * Copyright (C) 2005 Richard Purdie
254 + * See file CREDITS for list of people who contributed to this
257 + * This program is free software; you can redistribute it and/or
258 + * modify it under the terms of the GNU General Public License as
259 + * published by the Free Software Foundation; either version 2 of
260 + * the License, or (at your option) any later version.
262 + * This program is distributed in the hope that it will be useful,
263 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
264 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
265 + * GNU General Public License for more details.
267 + * You should have received a copy of the GNU General Public License
268 + * along with this program; if not, write to the Free Software
269 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
270 + * MA 02111-1307 USA
274 +#include <command.h>
276 +#include <version.h>
277 +#include <asm/arch/pxa-regs.h>
279 +#define GPIO_DFLT_LOW 0x400
280 +#define GPIO_DFLT_HIGH 0x800
282 +void pxa_gpio_mode(int gpio_mode)
284 + int gpio = gpio_mode & GPIO_MD_MASK_NR;
285 + int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
288 + if (gpio_mode & GPIO_DFLT_LOW)
289 + GPCR(gpio) = GPIO_bit(gpio);
290 + else if (gpio_mode & GPIO_DFLT_HIGH)
291 + GPSR(gpio) = GPIO_bit(gpio);
292 + if (gpio_mode & GPIO_MD_MASK_DIR)
293 + GPDR(gpio) |= GPIO_bit(gpio);
295 + GPDR(gpio) &= ~GPIO_bit(gpio);
296 + gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
297 + GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
300 +#define SPITZ_KEY_STROBE_NUM (11)
301 +#define SPITZ_KEY_SENSE_NUM (7)
303 +#define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000
304 +#define SPITZ_GPIO_G1_STROBE_BIT 0x00100000
305 +#define SPITZ_GPIO_G2_STROBE_BIT 0x01000000
306 +#define SPITZ_GPIO_G3_STROBE_BIT 0x00041880
307 +#define SPITZ_GPIO_G0_SENSE_BIT 0x00021000
308 +#define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4
309 +#define SPITZ_GPIO_G2_SENSE_BIT 0x08000000
310 +#define SPITZ_GPIO_G3_SENSE_BIT 0x00000000
312 +#define SPITZ_GPIO_KEY_STROBE0 88
313 +#define SPITZ_GPIO_KEY_STROBE1 23
314 +#define SPITZ_GPIO_KEY_STROBE2 24
315 +#define SPITZ_GPIO_KEY_STROBE3 25
316 +#define SPITZ_GPIO_KEY_STROBE4 26
317 +#define SPITZ_GPIO_KEY_STROBE5 27
318 +#define SPITZ_GPIO_KEY_STROBE6 52
319 +#define SPITZ_GPIO_KEY_STROBE7 103
320 +#define SPITZ_GPIO_KEY_STROBE8 107
321 +#define SPITZ_GPIO_KEY_STROBE9 108
322 +#define SPITZ_GPIO_KEY_STROBE10 114
324 +#define SPITZ_GPIO_KEY_SENSE0 12
325 +#define SPITZ_GPIO_KEY_SENSE1 17
326 +#define SPITZ_GPIO_KEY_SENSE2 91
327 +#define SPITZ_GPIO_KEY_SENSE3 34
328 +#define SPITZ_GPIO_KEY_SENSE4 36
329 +#define SPITZ_GPIO_KEY_SENSE5 38
330 +#define SPITZ_GPIO_KEY_SENSE6 39
332 +#define SPITZ_GPIO_ON_KEY (95)
336 +#define KB_ROWMASK(r) (1 << (r))
337 +#define SCANCODE(r,c) (((r)<<4) + (c) + 1)
338 +#define NR_SCANCODES ((KB_ROWS<<4) + 1)
340 +#define SCAN_INTERVAL (50) /* ms */
341 +#define HINGE_SCAN_INTERVAL (150) /* ms */
343 +#define KB_DISCHARGE_DELAY 10
344 +#define KB_ACTIVATE_DELAY 10
346 +static int spitz_strobes[] = {
347 + SPITZ_GPIO_KEY_STROBE0,
348 + SPITZ_GPIO_KEY_STROBE1,
349 + SPITZ_GPIO_KEY_STROBE2,
350 + SPITZ_GPIO_KEY_STROBE3,
351 + SPITZ_GPIO_KEY_STROBE4,
352 + SPITZ_GPIO_KEY_STROBE5,
353 + SPITZ_GPIO_KEY_STROBE6,
354 + SPITZ_GPIO_KEY_STROBE7,
355 + SPITZ_GPIO_KEY_STROBE8,
356 + SPITZ_GPIO_KEY_STROBE9,
357 + SPITZ_GPIO_KEY_STROBE10,
360 +static int spitz_senses[] = {
361 + SPITZ_GPIO_KEY_SENSE0,
362 + SPITZ_GPIO_KEY_SENSE1,
363 + SPITZ_GPIO_KEY_SENSE2,
364 + SPITZ_GPIO_KEY_SENSE3,
365 + SPITZ_GPIO_KEY_SENSE4,
366 + SPITZ_GPIO_KEY_SENSE5,
367 + SPITZ_GPIO_KEY_SENSE6,
370 +static inline void spitzkbd_discharge_all(void)
372 + /* STROBE All HiZ */
373 + GPCR0 = SPITZ_GPIO_G0_STROBE_BIT;
374 + GPDR0 &= ~SPITZ_GPIO_G0_STROBE_BIT;
375 + GPCR1 = SPITZ_GPIO_G1_STROBE_BIT;
376 + GPDR1 &= ~SPITZ_GPIO_G1_STROBE_BIT;
377 + GPCR2 = SPITZ_GPIO_G2_STROBE_BIT;
378 + GPDR2 &= ~SPITZ_GPIO_G2_STROBE_BIT;
379 + GPCR3 = SPITZ_GPIO_G3_STROBE_BIT;
380 + GPDR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
383 +static inline void spitzkbd_activate_all(void)
385 + /* STROBE ALL -> High */
386 + GPSR0 = SPITZ_GPIO_G0_STROBE_BIT;
387 + GPDR0 |= SPITZ_GPIO_G0_STROBE_BIT;
388 + GPSR1 = SPITZ_GPIO_G1_STROBE_BIT;
389 + GPDR1 |= SPITZ_GPIO_G1_STROBE_BIT;
390 + GPSR2 = SPITZ_GPIO_G2_STROBE_BIT;
391 + GPDR2 |= SPITZ_GPIO_G2_STROBE_BIT;
392 + GPSR3 = SPITZ_GPIO_G3_STROBE_BIT;
393 + GPDR3 |= SPITZ_GPIO_G3_STROBE_BIT;
395 + udelay(KB_DISCHARGE_DELAY);
398 +static inline void spitzkbd_activate_col(int col)
400 + int gpio = spitz_strobes[col];
401 + GPDR0 &= ~SPITZ_GPIO_G0_STROBE_BIT;
402 + GPDR1 &= ~SPITZ_GPIO_G1_STROBE_BIT;
403 + GPDR2 &= ~SPITZ_GPIO_G2_STROBE_BIT;
404 + GPDR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
405 + GPSR(gpio) = GPIO_bit(gpio);
406 + GPDR(gpio) |= GPIO_bit(gpio);
409 +static inline void spitzkbd_reset_col(int col)
411 + int gpio = spitz_strobes[col];
412 + GPDR0 &= ~SPITZ_GPIO_G0_STROBE_BIT;
413 + GPDR1 &= ~SPITZ_GPIO_G1_STROBE_BIT;
414 + GPDR2 &= ~SPITZ_GPIO_G2_STROBE_BIT;
415 + GPDR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
416 + GPCR(gpio) = GPIO_bit(gpio);
417 + GPDR(gpio) |= GPIO_bit(gpio);
420 +static inline int spitzkbd_get_row_status(int col)
422 + return ((GPLR0 >> 12) & 0x01) | ((GPLR0 >> 16) & 0x02)
423 + | ((GPLR2 >> 25) & 0x04) | ((GPLR1 << 1) & 0x08)
424 + | ((GPLR1 >> 0) & 0x10) | ((GPLR1 >> 1) & 0x60);
427 +static int spitzkbd_scankeyboard(void)
429 + unsigned int row, col, rowd;
430 + unsigned int num_pressed, pwrkey = ((GPLR(SPITZ_GPIO_ON_KEY) & GPIO_bit(SPITZ_GPIO_ON_KEY)) != 0);
434 + for (col = 0; col < KB_COLS; col++) {
435 + spitzkbd_discharge_all();
436 + udelay(KB_DISCHARGE_DELAY);
438 + spitzkbd_activate_col(col);
439 + udelay(KB_ACTIVATE_DELAY);
441 + rowd = spitzkbd_get_row_status(col);
442 + for (row = 0; row < KB_ROWS; row++) {
443 + unsigned int scancode, pressed;
445 + scancode = SCANCODE(row, col);
446 + pressed = rowd & KB_ROWMASK(row);
451 + spitzkbd_reset_col(col);
454 + spitzkbd_activate_all();
462 +void spitzkbd_init(void)
466 + /* Setup sense interrupts - RisingEdge Detect, sense lines as inputs */
467 + for (i = 0; i < SPITZ_KEY_SENSE_NUM; i++)
468 + pxa_gpio_mode(spitz_senses[i] | GPIO_IN);
470 + /* Set Strobe lines as outputs - set high */
471 + for (i = 0; i < SPITZ_KEY_STROBE_NUM; i++)
472 + pxa_gpio_mode(spitz_strobes[i] | GPIO_OUT | GPIO_DFLT_HIGH);
474 + pxa_gpio_mode(SPITZ_GPIO_ON_KEY | GPIO_IN);
477 +int do_testkey(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
484 + scan = spitzkbd_scankeyboard();
488 +// printf("Scan = %d\n", scan);
490 +// printf("Nothing!\n");
492 + return !(simple_strtol(argv[1], NULL, 10) == scan);
496 + testkey, 2, 1, do_testkey,
497 + "testkey - compare pressed key with arg\n",
500 diff -Nur u-boot-2006-04-18-1106/board/akita/lowlevel_init.S u-boot-2006-04-18-1106-new/board/akita/lowlevel_init.S
501 --- u-boot-2006-04-18-1106/board/akita/lowlevel_init.S 1970-01-01 00:00:00.000000000 +0000
502 +++ u-boot-2006-04-18-1106-new/board/akita/lowlevel_init.S 2006-07-05 11:19:44.000000000 +0000
505 + * board/akita/lowlevel_init.S
507 + * Configuration settings for the Sharp Zaurus SL-Cxx00.
509 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
511 + * This was originally from the Lubbock u-boot port and from BLOB with cleanup
513 + * NOTE: I haven't clean this up considerably, just enough to get it
514 + * running. See hal_platform_setup.h for the source. See
515 + * board/cradle/lowlevel_init.S for another PXA250 setup that is
518 + * See file CREDITS for list of people who contributed to this
521 + * This program is free software; you can redistribute it and/or
522 + * modify it under the terms of the GNU General Public License as
523 + * published by the Free Software Foundation; either version 2 of
524 + * the License, or (at your option) any later version.
526 + * This program is distributed in the hope that it will be useful,
527 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
528 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
529 + * GNU General Public License for more details.
531 + * You should have received a copy of the GNU General Public License
532 + * along with this program; if not, write to the Free Software
533 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
534 + * MA 02111-1307 USA
538 +#include <version.h>
539 +#include <asm/arch/pxa-regs.h>
541 +/* wait for coprocessor write complete */
543 + mrc p15,0,\reg,c2,c0,0
548 +/*********** Write out to HEX 7 segment leds *********/
553 +#define LEDCTL 0x08000040
554 +#define LEDDAT1 0x08000010
555 +#define LEDDAT2 0x08000014
569 + mov r10, #0xFFFFFFFF
581 + mov r10, #0xFFFFFFFF
603 +/***********************************/
609 +.globl lowlevel_init
614 +.globl set_turbo_mode
617 + /* Turn on turbo mode */
618 + mrc p14, 0, r2, c6, c0, 0
619 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
620 + mcr p14, 0, r2, c6, c0, 0
622 + /* Setup vectors */
624 + ldr r1, =TEXT_BASE+0x40
639 diff -Nur u-boot-2006-04-18-1106/board/akita/nand.c u-boot-2006-04-18-1106-new/board/akita/nand.c
640 --- u-boot-2006-04-18-1106/board/akita/nand.c 1970-01-01 00:00:00.000000000 +0000
641 +++ u-boot-2006-04-18-1106-new/board/akita/nand.c 2006-07-05 11:19:44.000000000 +0000
644 + * board/akita/nand.c
646 + * NAND driver for the Sharp Zaurus SL-Cxx00.
648 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
650 + * portions from mtd nand driver:
652 + * drivers/mtd/nand/sharpsl.c
654 + * Copyright (C) 2004 Richard Purdie
656 + * See file CREDITS for list of people who contributed to this
659 + * This program is free software; you can redistribute it and/or
660 + * modify it under the terms of the GNU General Public License as
661 + * published by the Free Software Foundation; either version 2 of
662 + * the License, or (at your option) any later version.
664 + * This program is distributed in the hope that it will be useful,
665 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
666 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
667 + * GNU General Public License for more details.
669 + * You should have received a copy of the GNU General Public License
670 + * along with this program; if not, write to the Free Software
671 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
672 + * MA 02111-1307 USA
678 +#if (CONFIG_COMMANDS & CFG_CMD_NAND)
681 +#include <linux/mtd/nand_ecc.h>
683 +static int sharpsl_io_base = CFG_NAND_BASE;
685 +/* register offset */
686 +#define ECCLPLB sharpsl_io_base+0x00 /* line parity 7 - 0 bit */
687 +#define ECCLPUB sharpsl_io_base+0x04 /* line parity 15 - 8 bit */
688 +#define ECCCP sharpsl_io_base+0x08 /* column parity 5 - 0 bit */
689 +#define ECCCNTR sharpsl_io_base+0x0C /* ECC byte counter */
690 +#define ECCCLRR sharpsl_io_base+0x10 /* cleare ECC */
691 +#define FLASHIO sharpsl_io_base+0x14 /* Flash I/O */
692 +#define FLASHCTL sharpsl_io_base+0x18 /* Flash Control */
694 +/* Flash control bit */
695 +#define FLRYBY (1 << 5)
696 +#define FLCE1 (1 << 4)
697 +#define FLWP (1 << 3)
698 +#define FLALE (1 << 2)
699 +#define FLCLE (1 << 1)
700 +#define FLCE0 (1 << 0)
702 +#define readb(address) *((volatile unsigned char *)(address))
703 +#define writeb(v, address) *((volatile unsigned char *)(address))=v
706 + * hardware specific access to control-lines
709 +sharpsl_nand_hwcontrol(struct mtd_info* mtd, int cmd)
712 + case NAND_CTL_SETCLE:
713 + writeb(readb(FLASHCTL) | FLCLE, FLASHCTL);
715 + case NAND_CTL_CLRCLE:
716 + writeb(readb(FLASHCTL) & ~FLCLE, FLASHCTL);
719 + case NAND_CTL_SETALE:
720 + writeb(readb(FLASHCTL) | FLALE, FLASHCTL);
722 + case NAND_CTL_CLRALE:
723 + writeb(readb(FLASHCTL) & ~FLALE, FLASHCTL);
726 + case NAND_CTL_SETNCE:
727 + writeb(readb(FLASHCTL) & ~(FLCE0|FLCE1), FLASHCTL);
729 + case NAND_CTL_CLRNCE:
730 + writeb(readb(FLASHCTL) | (FLCE0|FLCE1), FLASHCTL);
736 +sharpsl_nand_dev_ready(struct mtd_info* mtd)
738 + return !((readb(FLASHCTL) & FLRYBY) == 0);
742 +sharpsl_nand_enable_hwecc(struct mtd_info* mtd, int mode)
744 + writeb(0 ,ECCCLRR);
748 +sharpsl_nand_calculate_ecc(struct mtd_info* mtd, const u_char* dat,
751 + ecc_code[0] = ~readb(ECCLPUB);
752 + ecc_code[1] = ~readb(ECCLPLB);
753 + ecc_code[2] = (~readb(ECCCP) << 2) | 0x03;
754 + return readb(ECCCNTR) != 0;
757 +static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
759 +static struct nand_bbt_descr sharpsl_akita_bbt = {
763 + .pattern = scan_ff_pattern
766 +static struct nand_oobinfo akita_oobinfo = {
767 + .useecc = MTD_NANDECC_AUTOPLACE,
770 + 0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
771 + 0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
772 + 0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
773 + .oobfree = { {0x08, 0x09} }
777 + * Board-specific NAND initialization. The following members of the
778 + * argument are board-specific (per include/linux/mtd/nand.h):
779 + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
780 + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
781 + * - hwcontrol: hardwarespecific function for accesing control-lines
782 + * - dev_ready: hardwarespecific function for accesing device ready/busy line
783 + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
784 + * only be provided if a hardware ECC is available
785 + * - eccmode: mode of ecc, see defines
786 + * - chip_delay: chip dependent delay for transfering data from array to
788 + * - options: various chip options. They can partly be set to inform
789 + * nand_scan about special functionality. See the defines for further
791 + * Members with a "?" were not set in the merged testing-NAND branch,
792 + * so they are not set here either.
794 +void board_nand_init(struct nand_chip *nand)
796 + writeb(readb(FLASHCTL) | FLWP, FLASHCTL);
798 + nand->IO_ADDR_R = FLASHIO;
799 + nand->IO_ADDR_W = FLASHIO;
800 + nand->hwcontrol = sharpsl_nand_hwcontrol;
801 + nand->dev_ready = sharpsl_nand_dev_ready;
802 + nand->eccmode = NAND_ECC_HW3_256;
803 + nand->chip_delay = 15;
804 + nand->options = NAND_SAMSUNG_LP_OPTIONS;
805 + nand->badblock_pattern = &sharpsl_akita_bbt;
806 + nand->autooob = &akita_oobinfo;
807 + nand->enable_hwecc = sharpsl_nand_enable_hwecc;
808 + nand->calculate_ecc = sharpsl_nand_calculate_ecc;
809 + nand->correct_data = nand_correct_data;
811 +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
812 diff -Nur u-boot-2006-04-18-1106/board/akita/u-boot.lds u-boot-2006-04-18-1106-new/board/akita/u-boot.lds
813 --- u-boot-2006-04-18-1106/board/akita/u-boot.lds 1970-01-01 00:00:00.000000000 +0000
814 +++ u-boot-2006-04-18-1106-new/board/akita/u-boot.lds 2006-07-05 11:19:44.000000000 +0000
817 + * (C) Copyright 2000
818 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
820 + * See file CREDITS for list of people who contributed to this
823 + * This program is free software; you can redistribute it and/or
824 + * modify it under the terms of the GNU General Public License as
825 + * published by the Free Software Foundation; either version 2 of
826 + * the License, or (at your option) any later version.
828 + * This program is distributed in the hope that it will be useful,
829 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
830 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
831 + * GNU General Public License for more details.
833 + * You should have received a copy of the GNU General Public License
834 + * along with this program; if not, write to the Free Software
835 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
836 + * MA 02111-1307 USA
839 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
849 + cpu/pxa/start.o (.text)
854 + .rodata : { *(.rodata) }
857 + .data : { *(.data) }
863 + __u_boot_cmd_start = .;
864 + .u_boot_cmd : { *(.u_boot_cmd) }
865 + __u_boot_cmd_end = .;
872 diff -Nur u-boot-2006-04-18-1106/board/corgi/Makefile u-boot-2006-04-18-1106-new/board/corgi/Makefile
873 --- u-boot-2006-04-18-1106/board/corgi/Makefile 1970-01-01 00:00:00.000000000 +0000
874 +++ u-boot-2006-04-18-1106-new/board/corgi/Makefile 2006-07-05 11:19:44.000000000 +0000
877 +# board/corgi/Makefile
879 +# (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
881 +# (C) Copyright 2000
882 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
884 +# See file CREDITS for list of people who contributed to this
887 +# This program is free software; you can redistribute it and/or
888 +# modify it under the terms of the GNU General Public License as
889 +# published by the Free Software Foundation; either version 2 of
890 +# the License, or (at your option) any later version.
892 +# This program is distributed in the hope that it will be useful,
893 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
894 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
895 +# GNU General Public License for more details.
897 +# You should have received a copy of the GNU General Public License
898 +# along with this program; if not, write to the Free Software
899 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
903 +include $(TOPDIR)/config.mk
907 +OBJS := corgi.o nand.o kbd.o
908 +SOBJS := lowlevel_init.o
910 +$(LIB): $(OBJS) $(SOBJS)
911 + $(AR) crv $@ $(OBJS) $(SOBJS)
914 + rm -f $(SOBJS) $(OBJS)
917 + rm -f $(LIB) core *.bak .depend
919 +#########################################################################
921 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
922 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
926 +#########################################################################
927 diff -Nur u-boot-2006-04-18-1106/board/corgi/config.mk u-boot-2006-04-18-1106-new/board/corgi/config.mk
928 --- u-boot-2006-04-18-1106/board/corgi/config.mk 1970-01-01 00:00:00.000000000 +0000
929 +++ u-boot-2006-04-18-1106-new/board/corgi/config.mk 2006-07-05 11:19:44.000000000 +0000
931 +TEXT_BASE = 0xa1000000
932 diff -Nur u-boot-2006-04-18-1106/board/corgi/corgi.c u-boot-2006-04-18-1106-new/board/corgi/corgi.c
933 --- u-boot-2006-04-18-1106/board/corgi/corgi.c 1970-01-01 00:00:00.000000000 +0000
934 +++ u-boot-2006-04-18-1106-new/board/corgi/corgi.c 2006-07-05 11:19:44.000000000 +0000
937 + * board/corgi/corgi.c
939 + * Configuration settings for the Sharp Zaurus SL-C7x0/860.
941 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
943 + * portions from adsvix board configuration:
944 + * (C) Copyright 2004
945 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
946 + * (C) Copyright 2002
947 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
948 + * (C) Copyright 2002
949 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
950 + * Marius Groeger <mgroeger@sysgo.de>
952 + * See file CREDITS for list of people who contributed to this
955 + * This program is free software; you can redistribute it and/or
956 + * modify it under the terms of the GNU General Public License as
957 + * published by the Free Software Foundation; either version 2 of
958 + * the License, or (at your option) any later version.
960 + * This program is distributed in the hope that it will be useful,
961 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
962 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
963 + * GNU General Public License for more details.
965 + * You should have received a copy of the GNU General Public License
966 + * along with this program; if not, write to the Free Software
967 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
968 + * MA 02111-1307 USA
973 +/* ------------------------------------------------------------------------- */
976 + * Miscellaneous platform dependent initialisations
979 +int board_init (void)
981 + DECLARE_GLOBAL_DATA_PTR;
983 + /* memory and cpu-speed are setup before relocation */
984 + /* so we do _nothing_ here */
986 + /* arch number of Sharp Zaurus Corgi : MACH_TYPE_CORGI */
987 + gd->bd->bi_arch_number = 423;
989 + /* adress of boot parameters */
990 + gd->bd->bi_boot_params = 0xa0000100;
992 + /* set cpu turbo mode */
1000 +int board_late_init(void)
1002 + setenv("stdout", "serial");
1003 + setenv("stderr", "serial");
1008 +int dram_init (void)
1010 + DECLARE_GLOBAL_DATA_PTR;
1012 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
1013 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
1014 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
1015 + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
1016 + gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
1017 + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
1018 + gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
1019 + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
1023 diff -Nur u-boot-2006-04-18-1106/board/corgi/kbd.c u-boot-2006-04-18-1106-new/board/corgi/kbd.c
1024 --- u-boot-2006-04-18-1106/board/corgi/kbd.c 1970-01-01 00:00:00.000000000 +0000
1025 +++ u-boot-2006-04-18-1106-new/board/corgi/kbd.c 2006-07-05 11:19:44.000000000 +0000
1028 + * board/corgi/kbd.c
1030 + * Keyboard driver for the Sharp Zaurus SL-C7x0/860.
1032 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
1036 + * linux/drivers/input/keyboard/spitzkbd.c
1038 + * Keyboard driver for Sharp Corgi models (SL-C7xx)
1040 + * Copyright (C) 2005 Richard Purdie
1042 + * See file CREDITS for list of people who contributed to this
1045 + * This program is free software; you can redistribute it and/or
1046 + * modify it under the terms of the GNU General Public License as
1047 + * published by the Free Software Foundation; either version 2 of
1048 + * the License, or (at your option) any later version.
1050 + * This program is distributed in the hope that it will be useful,
1051 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1052 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1053 + * GNU General Public License for more details.
1055 + * You should have received a copy of the GNU General Public License
1056 + * along with this program; if not, write to the Free Software
1057 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1058 + * MA 02111-1307 USA
1061 +#include <common.h>
1062 +#include <command.h>
1063 +#include <config.h>
1064 +#include <version.h>
1065 +#include <asm/arch/pxa-regs.h>
1067 +#define GPIO_DFLT_LOW 0x400
1068 +#define GPIO_DFLT_HIGH 0x800
1070 +void pxa_gpio_mode(int gpio_mode)
1072 + int gpio = gpio_mode & GPIO_MD_MASK_NR;
1073 + int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
1076 + if (gpio_mode & GPIO_DFLT_LOW)
1077 + GPCR(gpio) = GPIO_bit(gpio);
1078 + else if (gpio_mode & GPIO_DFLT_HIGH)
1079 + GPSR(gpio) = GPIO_bit(gpio);
1080 + if (gpio_mode & GPIO_MD_MASK_DIR)
1081 + GPDR(gpio) |= GPIO_bit(gpio);
1083 + GPDR(gpio) &= ~GPIO_bit(gpio);
1084 + gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
1085 + GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
1089 + * Corgi Keyboard Definitions
1091 +#define CORGI_KEY_STROBE_NUM (12)
1092 +#define CORGI_KEY_SENSE_NUM (8)
1093 +#define CORGI_GPIO_ALL_STROBE_BIT (0x00003ffc)
1094 +#define CORGI_GPIO_HIGH_SENSE_BIT (0xfc000000)
1095 +#define CORGI_GPIO_HIGH_SENSE_RSHIFT (26)
1096 +#define CORGI_GPIO_LOW_SENSE_BIT (0x00000003)
1097 +#define CORGI_GPIO_LOW_SENSE_LSHIFT (6)
1098 +#define CORGI_GPIO_STROBE_BIT(a) GPIO_bit(66+(a))
1099 +#define CORGI_GPIO_SENSE_BIT(a) GPIO_bit(58+(a))
1100 +#define CORGI_GAFR_ALL_STROBE_BIT (0x0ffffff0)
1101 +#define CORGI_GAFR_HIGH_SENSE_BIT (0xfff00000)
1102 +#define CORGI_GAFR_LOW_SENSE_BIT (0x0000000f)
1103 +#define CORGI_GPIO_KEY_SENSE(a) (58+(a))
1104 +#define CORGI_GPIO_KEY_STROBE(a) (66+(a))
1106 +#define CORGI_GPIO_AK_INT (4) /* Headphone Jack Control Interrupt */
1110 +#define KB_ROWMASK(r) (1 << (r))
1111 +#define SCANCODE(r,c) ( ((r)<<4) + (c) + 1 )
1112 +/* zero code, 124 scancodes */
1113 +#define NR_SCANCODES ( SCANCODE(KB_ROWS-1,KB_COLS-1) +1 +1 )
1115 +#define SCAN_INTERVAL (50) /* ms */
1116 +#define HINGE_SCAN_INTERVAL (250) /* ms */
1118 +#define KB_DISCHARGE_DELAY 10
1119 +#define KB_ACTIVATE_DELAY 10
1121 +static inline void corgikbd_discharge_all(void)
1123 + /* STROBE All HiZ */
1124 + GPCR2 = CORGI_GPIO_ALL_STROBE_BIT;
1125 + GPDR2 &= ~CORGI_GPIO_ALL_STROBE_BIT;
1128 +static inline void corgikbd_activate_all(void)
1130 + /* STROBE ALL -> High */
1131 + GPSR2 = CORGI_GPIO_ALL_STROBE_BIT;
1132 + GPDR2 |= CORGI_GPIO_ALL_STROBE_BIT;
1134 + udelay(KB_DISCHARGE_DELAY);
1136 + /* Clear any interrupts we may have triggered when altering the GPIO lines */
1137 + GEDR1 = CORGI_GPIO_HIGH_SENSE_BIT;
1138 + GEDR2 = CORGI_GPIO_LOW_SENSE_BIT;
1141 +static inline void corgikbd_activate_col(int col)
1143 + /* STROBE col -> High, not col -> HiZ */
1144 + GPSR2 = CORGI_GPIO_STROBE_BIT(col);
1145 + GPDR2 = (GPDR2 & ~CORGI_GPIO_ALL_STROBE_BIT) | CORGI_GPIO_STROBE_BIT(col);
1148 +static inline void corgikbd_reset_col(int col)
1150 + /* STROBE col -> Low */
1151 + GPCR2 = CORGI_GPIO_STROBE_BIT(col);
1152 + /* STROBE col -> out, not col -> HiZ */
1153 + GPDR2 = (GPDR2 & ~CORGI_GPIO_ALL_STROBE_BIT) | CORGI_GPIO_STROBE_BIT(col);
1156 +#define GET_ROWS_STATUS(c) (((GPLR1 & CORGI_GPIO_HIGH_SENSE_BIT) >> CORGI_GPIO_HIGH_SENSE_RSHIFT) | ((GPLR2 & CORGI_GPIO_LOW_SENSE_BIT) << CORGI_GPIO_LOW_SENSE_LSHIFT))
1158 +static int corgikbd_scankeyboard(void)
1160 + unsigned int row, col, rowd;
1161 + unsigned int num_pressed;
1165 + for (col = 0; col < KB_COLS; col++) {
1166 + corgikbd_discharge_all();
1167 + udelay(KB_DISCHARGE_DELAY);
1169 + corgikbd_activate_col(col);
1170 + udelay(KB_ACTIVATE_DELAY);
1172 + rowd = GET_ROWS_STATUS(col);
1173 + for (row = 0; row < KB_ROWS; row++) {
1174 + unsigned int scancode, pressed;
1176 + scancode = SCANCODE(row, col);
1177 + pressed = rowd & KB_ROWMASK(row);
1182 + corgikbd_reset_col(col);
1185 + corgikbd_activate_all();
1190 +void corgikbd_init(void)
1194 + /* Setup sense interrupts - RisingEdge Detect, sense lines as inputs */
1195 + for (i = 0; i < CORGI_KEY_SENSE_NUM; i++)
1196 + pxa_gpio_mode(CORGI_GPIO_KEY_SENSE(i) | GPIO_IN);
1198 + /* Set Strobe lines as outputs - set high */
1199 + for (i = 0; i < CORGI_KEY_STROBE_NUM; i++)
1200 + pxa_gpio_mode(CORGI_GPIO_KEY_STROBE(i) | GPIO_OUT | GPIO_DFLT_HIGH);
1202 + /* Setup the headphone jack as an input */
1203 + pxa_gpio_mode(CORGI_GPIO_AK_INT | GPIO_IN);
1206 +int do_testkey(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
1213 + scan = corgikbd_scankeyboard();
1217 +// printf("Scan = %d\n", scan);
1219 +// printf("Nothing!\n");
1221 + return !(simple_strtol(argv[1], NULL, 10) == scan);
1225 + testkey, 2, 1, do_testkey,
1226 + "testkey - compare pressed key with arg\n",
1229 diff -Nur u-boot-2006-04-18-1106/board/corgi/lowlevel_init.S u-boot-2006-04-18-1106-new/board/corgi/lowlevel_init.S
1230 --- u-boot-2006-04-18-1106/board/corgi/lowlevel_init.S 1970-01-01 00:00:00.000000000 +0000
1231 +++ u-boot-2006-04-18-1106-new/board/corgi/lowlevel_init.S 2006-07-05 11:19:44.000000000 +0000
1234 + * board/corgi/lowlevel_init.S
1236 + * Configuration settings for the Sharp Zaurus SL-C7x0/860.
1238 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
1240 + * This was originally from the Lubbock u-boot port and from BLOB with cleanup
1242 + * NOTE: I haven't clean this up considerably, just enough to get it
1243 + * running. See hal_platform_setup.h for the source. See
1244 + * board/cradle/lowlevel_init.S for another PXA250 setup that is
1247 + * See file CREDITS for list of people who contributed to this
1250 + * This program is free software; you can redistribute it and/or
1251 + * modify it under the terms of the GNU General Public License as
1252 + * published by the Free Software Foundation; either version 2 of
1253 + * the License, or (at your option) any later version.
1255 + * This program is distributed in the hope that it will be useful,
1256 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1257 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1258 + * GNU General Public License for more details.
1260 + * You should have received a copy of the GNU General Public License
1261 + * along with this program; if not, write to the Free Software
1262 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1263 + * MA 02111-1307 USA
1266 +#include <config.h>
1267 +#include <version.h>
1268 +#include <asm/arch/pxa-regs.h>
1270 +/* wait for coprocessor write complete */
1272 + mrc p15,0,\reg,c2,c0,0
1277 +/*********** Write out to HEX 7 segment leds *********/
1279 +#undef DEBUG_HEXLOG
1281 +#ifdef DEBUG_HEXLOG
1282 +#define LEDCTL 0x08000040
1283 +#define LEDDAT1 0x08000010
1284 +#define LEDDAT2 0x08000014
1298 + mov r10, #0xFFFFFFFF
1310 + mov r10, #0xFFFFFFFF
1332 +/***********************************/
1338 +.globl lowlevel_init
1343 +.globl set_turbo_mode
1346 + /* Turn on turbo mode */
1347 + mrc p14, 0, r2, c6, c0, 0
1348 + orr r2, r2, #0x3 /* Turbo, Freq change */
1349 + mcr p14, 0, r2, c6, c0, 0
1352 + /* Setup vectors */
1353 + ldr r0, =TEXT_BASE
1354 + ldr r1, =TEXT_BASE+0x40
1369 diff -Nur u-boot-2006-04-18-1106/board/corgi/nand.c u-boot-2006-04-18-1106-new/board/corgi/nand.c
1370 --- u-boot-2006-04-18-1106/board/corgi/nand.c 1970-01-01 00:00:00.000000000 +0000
1371 +++ u-boot-2006-04-18-1106-new/board/corgi/nand.c 2006-07-05 11:19:44.000000000 +0000
1374 + * board/corgi/nand.c
1376 + * NAND driver for the Sharp Zaurus SL-C7x0/860.
1378 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
1380 + * portions from mtd nand driver:
1382 + * drivers/mtd/nand/sharpsl.c
1384 + * Copyright (C) 2004 Richard Purdie
1386 + * See file CREDITS for list of people who contributed to this
1389 + * This program is free software; you can redistribute it and/or
1390 + * modify it under the terms of the GNU General Public License as
1391 + * published by the Free Software Foundation; either version 2 of
1392 + * the License, or (at your option) any later version.
1394 + * This program is distributed in the hope that it will be useful,
1395 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1396 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1397 + * GNU General Public License for more details.
1399 + * You should have received a copy of the GNU General Public License
1400 + * along with this program; if not, write to the Free Software
1401 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1402 + * MA 02111-1307 USA
1405 +#include <common.h>
1408 +#if (CONFIG_COMMANDS & CFG_CMD_NAND)
1411 +#include <linux/mtd/nand_ecc.h>
1413 +static int sharpsl_io_base = CFG_NAND_BASE;
1415 +/* register offset */
1416 +#define ECCLPLB sharpsl_io_base+0x00 /* line parity 7 - 0 bit */
1417 +#define ECCLPUB sharpsl_io_base+0x04 /* line parity 15 - 8 bit */
1418 +#define ECCCP sharpsl_io_base+0x08 /* column parity 5 - 0 bit */
1419 +#define ECCCNTR sharpsl_io_base+0x0C /* ECC byte counter */
1420 +#define ECCCLRR sharpsl_io_base+0x10 /* cleare ECC */
1421 +#define FLASHIO sharpsl_io_base+0x14 /* Flash I/O */
1422 +#define FLASHCTL sharpsl_io_base+0x18 /* Flash Control */
1424 +/* Flash control bit */
1425 +#define FLRYBY (1 << 5)
1426 +#define FLCE1 (1 << 4)
1427 +#define FLWP (1 << 3)
1428 +#define FLALE (1 << 2)
1429 +#define FLCLE (1 << 1)
1430 +#define FLCE0 (1 << 0)
1432 +#define readb(address) *((volatile unsigned char *)(address))
1433 +#define writeb(v, address) *((volatile unsigned char *)(address))=v
1436 + * hardware specific access to control-lines
1439 +sharpsl_nand_hwcontrol(struct mtd_info* mtd, int cmd)
1442 + case NAND_CTL_SETCLE:
1443 + writeb(readb(FLASHCTL) | FLCLE, FLASHCTL);
1445 + case NAND_CTL_CLRCLE:
1446 + writeb(readb(FLASHCTL) & ~FLCLE, FLASHCTL);
1449 + case NAND_CTL_SETALE:
1450 + writeb(readb(FLASHCTL) | FLALE, FLASHCTL);
1452 + case NAND_CTL_CLRALE:
1453 + writeb(readb(FLASHCTL) & ~FLALE, FLASHCTL);
1456 + case NAND_CTL_SETNCE:
1457 + writeb(readb(FLASHCTL) & ~(FLCE0|FLCE1), FLASHCTL);
1459 + case NAND_CTL_CLRNCE:
1460 + writeb(readb(FLASHCTL) | (FLCE0|FLCE1), FLASHCTL);
1466 +sharpsl_nand_dev_ready(struct mtd_info* mtd)
1468 + return !((readb(FLASHCTL) & FLRYBY) == 0);
1472 +sharpsl_nand_enable_hwecc(struct mtd_info* mtd, int mode)
1474 + writeb(0 ,ECCCLRR);
1478 +sharpsl_nand_calculate_ecc(struct mtd_info* mtd, const u_char* dat,
1481 + ecc_code[0] = ~readb(ECCLPUB);
1482 + ecc_code[1] = ~readb(ECCLPLB);
1483 + ecc_code[2] = (~readb(ECCCP) << 2) | 0x03;
1484 + return readb(ECCCNTR) != 0;
1487 +static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
1489 +static struct nand_bbt_descr sharpsl_bbt = {
1493 + .pattern = scan_ff_pattern
1497 + * Board-specific NAND initialization. The following members of the
1498 + * argument are board-specific (per include/linux/mtd/nand.h):
1499 + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
1500 + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
1501 + * - hwcontrol: hardwarespecific function for accesing control-lines
1502 + * - dev_ready: hardwarespecific function for accesing device ready/busy line
1503 + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
1504 + * only be provided if a hardware ECC is available
1505 + * - eccmode: mode of ecc, see defines
1506 + * - chip_delay: chip dependent delay for transfering data from array to
1508 + * - options: various chip options. They can partly be set to inform
1509 + * nand_scan about special functionality. See the defines for further
1511 + * Members with a "?" were not set in the merged testing-NAND branch,
1512 + * so they are not set here either.
1514 +void board_nand_init(struct nand_chip *nand)
1516 + writeb(readb(FLASHCTL) | FLWP, FLASHCTL);
1518 + nand->IO_ADDR_R = FLASHIO;
1519 + nand->IO_ADDR_W = FLASHIO;
1520 + nand->hwcontrol = sharpsl_nand_hwcontrol;
1521 + nand->dev_ready = sharpsl_nand_dev_ready;
1522 + nand->eccmode = NAND_ECC_HW3_256;
1523 + nand->chip_delay = 15;
1524 + nand->badblock_pattern = &sharpsl_bbt;
1525 + nand->enable_hwecc = sharpsl_nand_enable_hwecc;
1526 + nand->calculate_ecc = sharpsl_nand_calculate_ecc;
1527 + nand->correct_data = nand_correct_data;
1529 +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
1530 diff -Nur u-boot-2006-04-18-1106/board/corgi/u-boot.lds u-boot-2006-04-18-1106-new/board/corgi/u-boot.lds
1531 --- u-boot-2006-04-18-1106/board/corgi/u-boot.lds 1970-01-01 00:00:00.000000000 +0000
1532 +++ u-boot-2006-04-18-1106-new/board/corgi/u-boot.lds 2006-07-05 11:19:44.000000000 +0000
1535 + * (C) Copyright 2000
1536 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1538 + * See file CREDITS for list of people who contributed to this
1541 + * This program is free software; you can redistribute it and/or
1542 + * modify it under the terms of the GNU General Public License as
1543 + * published by the Free Software Foundation; either version 2 of
1544 + * the License, or (at your option) any later version.
1546 + * This program is distributed in the hope that it will be useful,
1547 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1548 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1549 + * GNU General Public License for more details.
1551 + * You should have received a copy of the GNU General Public License
1552 + * along with this program; if not, write to the Free Software
1553 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1554 + * MA 02111-1307 USA
1557 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
1567 + cpu/pxa/start.o (.text)
1572 + .rodata : { *(.rodata) }
1575 + .data : { *(.data) }
1578 + .got : { *(.got) }
1581 + __u_boot_cmd_start = .;
1582 + .u_boot_cmd : { *(.u_boot_cmd) }
1583 + __u_boot_cmd_end = .;
1587 + .bss : { *(.bss) }
1590 diff -Nur u-boot-2006-04-18-1106/common/cmd_nand.c u-boot-2006-04-18-1106-new/common/cmd_nand.c
1591 --- u-boot-2006-04-18-1106/common/cmd_nand.c 2006-04-18 09:05:03.000000000 +0000
1592 +++ u-boot-2006-04-18-1106-new/common/cmd_nand.c 2006-07-05 11:19:44.000000000 +0000
1597 +#ifdef NAND_LOGICAL
1598 +/////////////////////////////////////////////////////////////////////
1600 +/////////////////////////////////////////////////////////////////////
1602 +#define NAND_NOOB_LOGADDR_00 8
1603 +#define NAND_NOOB_LOGADDR_01 9
1604 +#define NAND_NOOB_LOGADDR_10 10
1605 +#define NAND_NOOB_LOGADDR_11 11
1606 +#define NAND_NOOB_LOGADDR_20 12
1607 +#define NAND_NOOB_LOGADDR_21 13
1609 +static uint nand_get_logical_no(unsigned char *oob)
1611 + unsigned short us,bit;
1615 + if(oob[NAND_NOOB_LOGADDR_00] == oob[NAND_NOOB_LOGADDR_10] &&
1616 + oob[NAND_NOOB_LOGADDR_01] == oob[NAND_NOOB_LOGADDR_11]){
1617 + good0 = NAND_NOOB_LOGADDR_00;
1618 + good1 = NAND_NOOB_LOGADDR_01;
1620 + if(oob[NAND_NOOB_LOGADDR_10] == oob[NAND_NOOB_LOGADDR_20] &&
1621 + oob[NAND_NOOB_LOGADDR_11] == oob[NAND_NOOB_LOGADDR_21]){
1622 + good0 = NAND_NOOB_LOGADDR_10;
1623 + good1 = NAND_NOOB_LOGADDR_11;
1625 + if(oob[NAND_NOOB_LOGADDR_20] == oob[NAND_NOOB_LOGADDR_00] &&
1626 + oob[NAND_NOOB_LOGADDR_21] == oob[NAND_NOOB_LOGADDR_01]){
1627 + good0 = NAND_NOOB_LOGADDR_20;
1628 + good1 = NAND_NOOB_LOGADDR_21;
1633 + us = (((unsigned short)(oob[good0]) & 0x00ff) << 0) |
1634 + (((unsigned short)(oob[good1]) & 0x00ff) << 8);
1637 + for(bit = 0x0001; bit != 0; bit <<= 1){
1649 + return ((us & 0x07fe) >> 1);
1654 /* ------------------------------------------------------------------------- */
1657 @@ -245,6 +302,55 @@
1658 if (off == 0 && size == 0)
1661 +#ifdef NAND_LOGICAL
1662 + s = strchr(cmd, '.');
1664 + if (strcmp(s, ".logical") == 0) {
1665 + int blocks = NAND_LOGICAL_SIZE / nand->erasesize;
1666 + ulong *log2phy = malloc(blocks * sizeof(ulong));
1667 + u_char *oobuf = malloc(nand->oobblock + nand->oobsize);
1671 + for (i = 0; i < blocks; i++)
1672 + log2phy[i] = (uint) -1;
1674 + for (i = 0; i < blocks; i++) {
1675 + ret = nand_read_raw(nand, oobuf, offset, nand->oobblock, nand->oobsize);
1677 + int log_no = nand_get_logical_no(oobuf + nand->oobblock);
1678 + if (((int)log_no >= 0) && (log_no < blocks)) {
1679 + log2phy[log_no] = offset;
1680 + //printf("NAND logical - %08X -> %04X\n", offset, log_no);
1683 + offset += nand->erasesize;
1686 + for (i = 0; i < size / nand->erasesize; i++) {
1687 + ulong sz = nand->erasesize;
1688 + offset = log2phy[off / nand->erasesize];
1689 + if ((int)offset < 0) {
1690 + printf("NAND logical - offset %08X not found\n", off);
1693 + //printf("NAND logical - %04X -> %08X\n", off / nand->erasesize, offset);
1694 + ret = nand_read(nand, offset, &sz, (u_char *)addr);
1696 + printf("NAND logical - offset %08X, read error\n", off);
1699 + off += nand->erasesize;
1700 + addr += nand->erasesize;
1702 + printf(" %d bytes read from NAND logical\n", size);
1705 + return ret == 0 ? 0 : 1;
1710 i = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
1711 printf("\nNAND %s: device %d offset %u, size %u ... ",
1712 i ? "read" : "write", nand_curr_device, off, size);
1713 diff -Nur u-boot-2006-04-18-1106/cpu/pxa/config.mk u-boot-2006-04-18-1106-new/cpu/pxa/config.mk
1714 --- u-boot-2006-04-18-1106/cpu/pxa/config.mk 2006-04-18 09:05:03.000000000 +0000
1715 +++ u-boot-2006-04-18-1106-new/cpu/pxa/config.mk 2006-07-05 11:19:44.000000000 +0000
1720 -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
1722 +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 -fomit-frame-pointer
1724 #PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
1725 PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale
1727 # Supply options according to compiler version
1729 # ========================================================================
1730 -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
1731 +#PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
1732 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
1733 diff -Nur u-boot-2006-04-18-1106/cpu/pxa/start.S u-boot-2006-04-18-1106-new/cpu/pxa/start.S
1734 --- u-boot-2006-04-18-1106/cpu/pxa/start.S 2006-04-18 09:05:03.000000000 +0000
1735 +++ u-boot-2006-04-18-1106-new/cpu/pxa/start.S 2006-07-05 11:19:44.000000000 +0000
1740 +_reset: .word reset
1741 _undefined_instruction: .word undefined_instruction
1742 _software_interrupt: .word software_interrupt
1743 _prefetch_abort: .word prefetch_abort
1744 diff -Nur u-boot-2006-04-18-1106/fs/cramfs/cramfs.c u-boot-2006-04-18-1106-new/fs/cramfs/cramfs.c
1745 --- u-boot-2006-04-18-1106/fs/cramfs/cramfs.c 2006-04-18 09:05:03.000000000 +0000
1746 +++ u-boot-2006-04-18-1106-new/fs/cramfs/cramfs.c 2006-07-05 11:19:44.000000000 +0000
1749 /* CPU address space offset calculation macro, struct part_info offset is
1750 * device address space offset, so we need to shift it by a device start address. */
1751 +#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
1752 extern flash_info_t flash_info[];
1753 #define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0])
1755 +static struct cramfs_super super_fake;
1756 +#define PART_OFFSET(x) (&super_fake)
1759 static int cramfs_read_super (struct part_info *info)
1761 diff -Nur u-boot-2006-04-18-1106/include/asm-arm/arch-pxa/pxa-regs.h u-boot-2006-04-18-1106-new/include/asm-arm/arch-pxa/pxa-regs.h
1762 --- u-boot-2006-04-18-1106/include/asm-arm/arch-pxa/pxa-regs.h 2006-04-18 09:05:03.000000000 +0000
1763 +++ u-boot-2006-04-18-1106-new/include/asm-arm/arch-pxa/pxa-regs.h 2006-07-05 11:19:44.000000000 +0000
1764 @@ -1269,15 +1269,16 @@
1765 #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
1766 #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
1768 -#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
1769 -#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
1770 -#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
1771 -#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
1772 -#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
1773 -#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
1774 -#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
1775 -#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \
1776 - ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
1777 +#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
1778 +#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
1779 +#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
1780 +#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
1781 +#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
1782 +#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
1783 +#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
1784 +#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
1785 + ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
1789 #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
1790 diff -Nur u-boot-2006-04-18-1106/include/configs/akita.h u-boot-2006-04-18-1106-new/include/configs/akita.h
1791 --- u-boot-2006-04-18-1106/include/configs/akita.h 1970-01-01 00:00:00.000000000 +0000
1792 +++ u-boot-2006-04-18-1106-new/include/configs/akita.h 2006-07-13 11:00:46.000000000 +0000
1795 + * include/configs/akita.h
1797 + * Configuration settings for the Sharp Zaurus SL-C1000/C3100.
1799 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
1801 + * portions from adsvix board configuration:
1802 + * (C) Copyright 2004
1803 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
1804 + * (C) Copyright 2002
1805 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
1806 + * (C) Copyright 2002
1807 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
1808 + * Marius Groeger <mgroeger@sysgo.de>
1810 + * See file CREDITS for list of people who contributed to this
1813 + * This program is free software; you can redistribute it and/or
1814 + * modify it under the terms of the GNU General Public License as
1815 + * published by the Free Software Foundation; either version 2 of
1816 + * the License, or (at your option) any later version.
1818 + * This program is distributed in the hope that it will be useful,
1819 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1820 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1821 + * GNU General Public License for more details.
1823 + * You should have received a copy of the GNU General Public License
1824 + * along with this program; if not, write to the Free Software
1825 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1826 + * MA 02111-1307 USA
1832 +#define CONFIG_SKIP_LOWLEVEL_INIT
1834 +#undef SKIP_CONFIG_RELOCATE_UBOOT
1836 +#undef CONFIG_HARD_I2C
1839 + * High Level Configuration Options
1840 + * (easy to change)
1842 +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
1843 +#define CONFIG_AKITA 1 /* on Sharp Zaurus Akita */
1844 +//#define CONFIG_MMC 1
1845 +#define BOARD_LATE_INIT 1
1847 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
1852 + * Size of malloc() pool
1854 +//#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
1855 +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
1856 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
1859 + * select serial console configuration
1861 +#define CONFIG_FFUART 1 /* we use FFUART on Mainstone */
1863 +/* allow to overwrite serial and ethaddr */
1864 +#define CONFIG_BAUDRATE 115200
1865 +//#define CONFIG_DOS_PARTITION 1
1867 +#undef CONFIG_SHOW_BOOT_PROGRESS
1870 +#define CONFIG_BOOTDELAY 1
1871 +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n"
1873 +#define CONFIG_BOOTCOMMAND \
1874 + "if testkey 101 ; " \
1876 + "nand read.logical 0xa1000000 0x00060000 0x00540000; " \
1877 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/ram rw fbcon=rotate:1 ramdisk_size=8192; " \
1880 + "if testkey 2 ; " \
1882 + "nand read.logical 0xa1000000 0x005a0000 0x00160000; " \
1883 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/mmcblk0p1 fbcon=rotate:1; " \
1886 + "if testkey 18 ; " \
1888 + "nand read.logical 0xa1000000 0x005a0000 0x00160000; " \
1889 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/hda1 fbcon=rotate:1; " \
1892 + "if testkey 3 ; " \
1894 + "nand read.logical 0xa1000000 0x005a0000 0x00160000; " \
1895 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/hdc1 fbcon=rotate:1; " \
1898 + "nand read.logical 0xa1000000 0x005a0000 0x00160000; " \
1899 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/mtdblock2 rootfstype=jffs2 fbcon=rotate:1; " \
1902 +#define CONFIG_BOOTCOMMAND "" // "run boot_flash"
1905 +#define CONFIG_BOOTARGS "console=ttyS0,115200 console=tty1 root=/dev/ram rw fbcon=rotate:1 ramdisk_size=8192"
1906 +#define CONFIG_SETUP_MEMORY_TAGS 1
1907 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
1908 +#define CONFIG_INITRD_TAG 1
1910 +#define CONFIG_COMMANDS (( \
1911 + CONFIG_CMD_DFL | \
1922 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
1923 +#include <cmd_confdefs.h>
1926 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
1927 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
1928 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
1932 + * Miscellaneous configurable options
1934 +#define CFG_HUSH_PARSER 1
1935 +#define CFG_PROMPT_HUSH_PS2 "> "
1937 +#define CFG_LONGHELP /* undef to save memory */
1938 +#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
1940 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
1941 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
1942 +#define CFG_MAXARGS 16 /* max number of command args */
1943 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
1944 +#define CFG_DEVICE_NULLDEV 1
1946 +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
1947 +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
1949 +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
1951 +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */
1953 +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
1954 +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
1956 + /* valid baudrates */
1957 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
1959 +#define CFG_MMC_BASE 0xF0000000
1964 + * The stack sizes are set up in start.S using the settings below
1966 +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
1967 +#ifdef CONFIG_USE_IRQ
1968 +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
1969 +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
1973 + * Physical Memory Map
1975 +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
1976 +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
1977 +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
1978 +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
1979 +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
1980 +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
1981 +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
1982 +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
1983 +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
1985 +#define PHYS_FLASH_1 0xd4000000 /* Flash Bank #1 */
1987 +#define CFG_DRAM_BASE 0xa0000000
1988 +#define CFG_DRAM_SIZE 0x04000000
1990 +#define CFG_FLASH_BASE PHYS_FLASH_1
1993 + * GPIO settings for Mainstone
1996 +#define CFG_GPSR0_VAL 0x00708800
1997 +#define CFG_GPSR1_VAL 0x03cf0002
1998 +#define CFG_GPSR2_VAL 0x0021FC00
1999 +#define CFG_GPSR3_VAL 0x00000000
2001 +#define CFG_GPCR0_VAL 0x00001000
2002 +#define CFG_GPCR1_VAL 0x00000000
2003 +#define CFG_GPCR2_VAL 0x00000000
2004 +#define CFG_GPCR3_VAL 0x00000000
2006 +#define CFG_GPDR0_VAL 0xC27B9C04
2007 +#define CFG_GPDR1_VAL 0x00EFAA83
2008 +#define CFG_GPDR2_VAL 0x0E23FC00
2009 +#define CFG_GPDR3_VAL 0x001E1F81
2011 +#define CFG_GAFR0_L_VAL 0x94F00000
2012 +#define CFG_GAFR0_U_VAL 0x015A859A
2013 +#define CFG_GAFR1_L_VAL 0x999A955A
2014 +#define CFG_GAFR1_U_VAL 0x0005A4AA
2015 +#define CFG_GAFR2_L_VAL 0x6AA00000
2016 +#define CFG_GAFR2_U_VAL 0x55A8041A
2017 +#define CFG_GAFR3_L_VAL 0x56AA955A
2018 +#define CFG_GAFR3_U_VAL 0x00000001
2020 +#define CFG_PSSR_VAL 0x20 // ???????????
2023 + * PCMCIA and CF Interfaces
2025 +#define CFG_MECR_VAL 0x00000001
2026 +#define CFG_MCMEM0_VAL 0x00010204
2027 +#define CFG_MCMEM1_VAL 0x00010204
2028 +#define CFG_MCATT0_VAL 0x00010204
2029 +#define CFG_MCATT1_VAL 0x00010204
2030 +#define CFG_MCIO0_VAL 0x0000c108
2031 +#define CFG_MCIO1_VAL 0x0001c108
2033 +//#define CONFIG_PXA_PCMCIA 1
2034 +//#define CONFIG_PXA_IDE 1
2036 +#define CONFIG_PCMCIA_SLOT_A 1
2037 +/* just to keep build system happy */
2039 +#define CFG_PCMCIA_MEM_ADDR 0x28000000
2040 +#define CFG_PCMCIA_MEM_SIZE 0x04000000
2042 +#define CFG_IDE_MAXBUS 1
2043 +/* max. 1 IDE bus */
2044 +#define CFG_IDE_MAXDEVICE 1
2045 +/* max. 1 drive per IDE bus */
2047 +#define CFG_ATA_IDE0_OFFSET 0x0000
2049 +#define CFG_ATA_BASE_ADDR 0x20000000
2051 +/* Offset for data I/O */
2052 +#define CFG_ATA_DATA_OFFSET 0x1f0
2054 +/* Offset for normal register accesses */
2055 +#define CFG_ATA_REG_OFFSET 0x1f0
2057 +/* Offset for alternate registers */
2058 +#define CFG_ATA_ALT_OFFSET 0x3f0
2060 +#define CFG_NO_FLASH 1
2061 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
2062 +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
2064 +/*-----------------------------------------------------------------------
2065 + * NAND-FLASH stuff
2066 + *-----------------------------------------------------------------------
2068 +#undef CFG_NAND_LEGACY
2070 +/* NAND debugging */
2071 +//#define CONFIG_MTD_DEBUG
2072 +//#define CONFIG_MTD_DEBUG_VERBOSE 3
2074 +#define CFG_NAND_BASE 0xd4000000
2075 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
2076 +#define NAND_MAX_CHIPS 1
2078 +//#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
2079 +//#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
2081 +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
2082 +#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
2085 + * JFFS2 partitions
2088 +/* No command line, one static partition */
2089 +//#undef CONFIG_JFFS2_CMDLINE
2090 +//#define CONFIG_JFFS2_DEV "nand0"
2091 +//#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
2092 +//#define CONFIG_JFFS2_PART_OFFSET 0x00060000
2094 +/* mtdparts command line support */
2095 +/* Note: fake mtd_id used, no linux mtd map file */
2097 +#define CONFIG_JFFS2_CMDLINE
2098 +#define MTDIDS_DEFAULT "nand0=laze-0"
2099 +//#define MTDPARTS_DEFAULT "mtdparts=laze-0:256k(uboot),128k(env),-(jffs2)"
2100 +#define MTDPARTS_DEFAULT "mtdparts=laze-0:7168k(Logical),-(JFFS2)"
2103 + * SHARP SL NAND logical partition
2105 +#define NAND_LOGICAL 1
2106 +#define NAND_LOGICAL_SIZE 0x700000
2112 +#define CFG_ENV_IS_IN_NAND 1
2113 +#define CFG_ENV_OFFSET 0x40000
2114 +//#define CFG_ENV_OFFSET_REDUND 0x44000
2115 +#define CFG_ENV_SIZE 0x20000
2117 +#endif /* __CONFIG_H */
2118 diff -Nur u-boot-2006-04-18-1106/include/configs/corgi.h u-boot-2006-04-18-1106-new/include/configs/corgi.h
2119 --- u-boot-2006-04-18-1106/include/configs/corgi.h 1970-01-01 00:00:00.000000000 +0000
2120 +++ u-boot-2006-04-18-1106-new/include/configs/corgi.h 2006-07-13 11:19:04.000000000 +0000
2123 + * include/configs/corgi.h
2125 + * Configuration settings for the Sharp Zaurus SL-C7x0/C860.
2127 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
2129 + * portions from adsvix board configuration:
2130 + * (C) Copyright 2004
2131 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
2132 + * (C) Copyright 2002
2133 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
2134 + * (C) Copyright 2002
2135 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
2136 + * Marius Groeger <mgroeger@sysgo.de>
2138 + * See file CREDITS for list of people who contributed to this
2141 + * This program is free software; you can redistribute it and/or
2142 + * modify it under the terms of the GNU General Public License as
2143 + * published by the Free Software Foundation; either version 2 of
2144 + * the License, or (at your option) any later version.
2146 + * This program is distributed in the hope that it will be useful,
2147 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2148 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2149 + * GNU General Public License for more details.
2151 + * You should have received a copy of the GNU General Public License
2152 + * along with this program; if not, write to the Free Software
2153 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2154 + * MA 02111-1307 USA
2160 +#define CONFIG_SKIP_LOWLEVEL_INIT
2162 +#undef SKIP_CONFIG_RELOCATE_UBOOT
2164 +#undef CONFIG_HARD_I2C
2167 + * High Level Configuration Options
2168 + * (easy to change)
2170 +#define CONFIG_PXA250 1 /* This is an PXA255 CPU */
2171 +#define CONFIG_CORGI 1 /* on Sharp Zaurus Corgi */
2172 +//#define CONFIG_MMC 1
2173 +#define BOARD_LATE_INIT 1
2175 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
2180 + * Size of malloc() pool
2182 +//#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
2183 +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
2184 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
2187 + * select serial console configuration
2189 +#define CONFIG_FFUART 1 /* we use FFUART on Mainstone */
2191 +/* allow to overwrite serial and ethaddr */
2192 +#define CONFIG_BAUDRATE 115200
2193 +//#define CONFIG_DOS_PARTITION 1
2195 +#undef CONFIG_SHOW_BOOT_PROGRESS
2198 +#define CONFIG_BOOTDELAY 1
2199 +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n"
2201 +#define CONFIG_BOOTCOMMAND \
2202 + "if testkey 101 ; " \
2204 + "nand read.logical 0xa0800000 0x00060000 0x00540000; " \
2205 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/ram rw ramdisk_size=8192; " \
2208 + "if testkey 2 ; " \
2210 + "nand read.logical 0xa0800000 0x005a0000 0x00160000; " \
2211 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/mmcblk0p1; " \
2214 + "if testkey 18 ; " \
2216 + "nand read.logical 0xa0800000 0x005a0000 0x00160000; " \
2217 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/hda1; " \
2220 + "if testkey 3 ; " \
2222 + "nand read.logical 0xa0800000 0x005a0000 0x00160000; " \
2223 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/hdc1; " \
2226 + "nand read.logical 0xa0800000 0x005a0000 0x00160000; " \
2227 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/mtdblock2 rootfstype=jffs2; " \
2230 +#define CONFIG_BOOTCOMMAND "" // "run boot_flash"
2233 +#define CONFIG_BOOTARGS "console=ttyS0,115200 console=tty1 root=/dev/ram rw ramdisk_size=8192"
2234 +#define CONFIG_SETUP_MEMORY_TAGS 1
2235 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
2236 +#define CONFIG_INITRD_TAG 1
2238 +#define CONFIG_COMMANDS (( \
2239 + CONFIG_CMD_DFL | \
2250 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
2251 +#include <cmd_confdefs.h>
2254 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
2255 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
2256 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
2260 + * Miscellaneous configurable options
2262 +#define CFG_HUSH_PARSER 1
2263 +#define CFG_PROMPT_HUSH_PS2 "> "
2265 +#define CFG_LONGHELP /* undef to save memory */
2266 +#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
2268 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
2269 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
2270 +#define CFG_MAXARGS 16 /* max number of command args */
2271 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
2272 +#define CFG_DEVICE_NULLDEV 1
2274 +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
2275 +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
2277 +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
2279 +#define CFG_LOAD_ADDR 0xa0800000 /* default load address */
2281 +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
2282 +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
2284 + /* valid baudrates */
2285 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
2287 +#define CFG_MMC_BASE 0xF0000000
2292 + * The stack sizes are set up in start.S using the settings below
2294 +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
2295 +#ifdef CONFIG_USE_IRQ
2296 +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
2297 +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
2301 + * Physical Memory Map
2303 +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
2304 +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
2305 +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
2306 +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
2307 +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
2308 +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
2309 +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
2310 +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
2311 +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
2313 +#define PHYS_FLASH_1 0xd4000000 /* Flash Bank #1 */
2315 +#define CFG_DRAM_BASE 0xa0000000
2316 +#define CFG_DRAM_SIZE 0x04000000
2318 +#define CFG_FLASH_BASE PHYS_FLASH_1
2321 + * GPIO settings for Mainstone
2324 +#define CFG_GPSR0_VAL 0x00708800
2325 +#define CFG_GPSR1_VAL 0x03cf0002
2326 +#define CFG_GPSR2_VAL 0x0021FC00
2327 +#define CFG_GPSR3_VAL 0x00000000
2329 +#define CFG_GPCR0_VAL 0x00001000
2330 +#define CFG_GPCR1_VAL 0x00000000
2331 +#define CFG_GPCR2_VAL 0x00000000
2332 +#define CFG_GPCR3_VAL 0x00000000
2334 +#define CFG_GPDR0_VAL 0xC27B9C04
2335 +#define CFG_GPDR1_VAL 0x00EFAA83
2336 +#define CFG_GPDR2_VAL 0x0E23FC00
2337 +#define CFG_GPDR3_VAL 0x001E1F81
2339 +#define CFG_GAFR0_L_VAL 0x94F00000
2340 +#define CFG_GAFR0_U_VAL 0x015A859A
2341 +#define CFG_GAFR1_L_VAL 0x999A955A
2342 +#define CFG_GAFR1_U_VAL 0x0005A4AA
2343 +#define CFG_GAFR2_L_VAL 0x6AA00000
2344 +#define CFG_GAFR2_U_VAL 0x55A8041A
2345 +#define CFG_GAFR3_L_VAL 0x56AA955A
2346 +#define CFG_GAFR3_U_VAL 0x00000001
2348 +#define CFG_PSSR_VAL 0x20 // ???????????
2351 + * PCMCIA and CF Interfaces
2353 +#define CFG_MECR_VAL 0x00000001
2354 +#define CFG_MCMEM0_VAL 0x00010204
2355 +#define CFG_MCMEM1_VAL 0x00010204
2356 +#define CFG_MCATT0_VAL 0x00010204
2357 +#define CFG_MCATT1_VAL 0x00010204
2358 +#define CFG_MCIO0_VAL 0x0000c108
2359 +#define CFG_MCIO1_VAL 0x0001c108
2361 +//#define CONFIG_PXA_PCMCIA 1
2362 +//#define CONFIG_PXA_IDE 1
2364 +#define CONFIG_PCMCIA_SLOT_A 1
2365 +/* just to keep build system happy */
2367 +#define CFG_PCMCIA_MEM_ADDR 0x28000000
2368 +#define CFG_PCMCIA_MEM_SIZE 0x04000000
2370 +#define CFG_IDE_MAXBUS 1
2371 +/* max. 1 IDE bus */
2372 +#define CFG_IDE_MAXDEVICE 1
2373 +/* max. 1 drive per IDE bus */
2375 +#define CFG_ATA_IDE0_OFFSET 0x0000
2377 +#define CFG_ATA_BASE_ADDR 0x20000000
2379 +/* Offset for data I/O */
2380 +#define CFG_ATA_DATA_OFFSET 0x1f0
2382 +/* Offset for normal register accesses */
2383 +#define CFG_ATA_REG_OFFSET 0x1f0
2385 +/* Offset for alternate registers */
2386 +#define CFG_ATA_ALT_OFFSET 0x3f0
2388 +#define CFG_NO_FLASH 1
2389 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
2390 +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
2392 +/*-----------------------------------------------------------------------
2393 + * NAND-FLASH stuff
2394 + *-----------------------------------------------------------------------
2396 +#undef CFG_NAND_LEGACY
2398 +/* NAND debugging */
2399 +//#define CONFIG_MTD_DEBUG
2400 +//#define CONFIG_MTD_DEBUG_VERBOSE 3
2402 +#define CFG_NAND_BASE 0xd4000000
2403 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
2404 +#define NAND_MAX_CHIPS 1
2406 +//#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
2407 +//#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
2409 +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
2410 +#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
2412 +#define NAND_ALLOW_ERASE_ALL 1
2415 + * JFFS2 partitions
2418 +/* No command line, one static partition */
2419 +//#undef CONFIG_JFFS2_CMDLINE
2420 +//#define CONFIG_JFFS2_DEV "nand0"
2421 +//#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
2422 +//#define CONFIG_JFFS2_PART_OFFSET 0x00060000
2424 +/* mtdparts command line support */
2425 +/* Note: fake mtd_id used, no linux mtd map file */
2427 +#define CONFIG_JFFS2_CMDLINE
2428 +#define MTDIDS_DEFAULT "nand0=laze-0"
2429 +//#define MTDPARTS_DEFAULT "mtdparts=laze-0:256k(uboot),128k(env),-(jffs2)"
2430 +#define MTDPARTS_DEFAULT "mtdparts=laze-0:7168k(Logical),-(JFFS2)"
2433 + * SHARP SL NAND logical partition
2435 +#define NAND_LOGICAL 1
2436 +#define NAND_LOGICAL_SIZE 0x700000
2442 +#define CFG_ENV_IS_IN_NAND 1
2443 +#define CFG_ENV_OFFSET 0x40000
2444 +//#define CFG_ENV_OFFSET_REDUND 0x44000
2445 +#define CFG_ENV_SIZE 0x20000
2447 +#endif /* __CONFIG_H */
2448 --- s/examples/Makefile.orig 2006-12-09 15:08:45.000000000 +0600
2449 +++ s/examples/Makefile 2006-12-09 15:09:00.000000000 +0600
2451 include $(TOPDIR)/config.mk
2453 SREC = hello_world.srec
2454 -BIN = hello_world.bin hello_world
2455 +BIN = hello_world hello_world.bin
2457 ifeq ($(CPU),mpc8xx)
2458 SREC = test_burst.srec
2463 -all: .depend $(OBJS) $(LIB) $(SREC) $(BIN)
2464 +all: .depend $(OBJS) $(LIB) $(BIN) $(SREC)
2466 #########################################################################
2467 $(LIB): .depend $(LIBOBJS)
2468 diff -Nur u-boot-2006-04-18-1106/CREDITS u-boot-2006-04-18-1106-new/CREDITS
2469 --- u-boot-2006-04-18-1106/CREDITS 2006-04-18 09:05:03.000000000 +0000
2470 +++ u-boot-2006-04-18-1106-new/CREDITS 2006-07-05 11:19:44.000000000 +0000
2472 E: jonathan.debruyne@siemens.atea.be
2473 D: Port to Siemens IAD210 board
2475 +N: Alexander Chukov
2476 +E: sash@pdaXrom.org
2477 +D: initial support for Sharp Zaurus SL-C1000/3100
2478 +D: initial support for Sharp Zaurus SL-C7x0/C860
2479 +W: http://www.pdaXrom.org
2483 D: Support for A3000 SBC board
2484 diff -Nur u-boot-2006-04-18-1106/MAINTAINERS u-boot-2006-04-18-1106-new/MAINTAINERS
2485 --- u-boot-2006-04-18-1106/MAINTAINERS 2006-04-18 09:05:03.000000000 +0000
2486 +++ u-boot-2006-04-18-1106-new/MAINTAINERS 2006-07-05 11:19:44.000000000 +0000
2487 @@ -379,6 +379,11 @@
2489 AT91RM9200DK at91rm9200
2491 +Alexander Chukov <sash@pdaXrom.org>
2496 George G. Davis <gdavis@mvista.com>
2499 diff -Nur u-boot-2006-04-18-1106/MAKEALL u-boot-2006-04-18-1106-new/MAKEALL
2500 --- u-boot-2006-04-18-1106/MAKEALL 2006-04-18 09:05:03.000000000 +0000
2501 +++ u-boot-2006-04-18-1106-new/MAKEALL 2006-07-05 11:19:44.000000000 +0000
2503 adsvix cerf250 cradle csb226 \
2504 delta innokom lubbock pxa255_idp \
2505 wepep250 xaeniax xm250 xsengine \
2507 + zylonite akita corgi \
2511 diff -Nur u-boot-2006-04-18-1106/Makefile u-boot-2006-04-18-1106-new/Makefile
2512 --- u-boot-2006-04-18-1106/Makefile 2006-04-18 09:05:03.000000000 +0000
2513 +++ u-boot-2006-04-18-1106-new/Makefile 2006-07-05 11:19:44.000000000 +0000
2515 CROSS_COMPILE = powerpc-linux-
2518 -CROSS_COMPILE = arm-linux-
2519 +CROSS_COMPILE = armv5tel-linux-
2522 ifeq ($(HOSTARCH),i386)
2523 @@ -1709,6 +1709,12 @@
2525 @./mkconfig $(@:_config=) arm pxa zylonite
2527 +akita_config : unconfig
2528 + @./mkconfig $(@:_config=) arm pxa akita
2530 +corgi_config : unconfig
2531 + @./mkconfig $(@:_config=) arm pxa corgi
2533 #########################################################################
2535 #########################################################################
2536 diff -Nur u-boot-2006-04-18-1106/README u-boot-2006-04-18-1106-new/README
2537 --- u-boot-2006-04-18-1106/README 2006-04-18 09:05:03.000000000 +0000
2538 +++ u-boot-2006-04-18-1106-new/README 2006-07-05 11:19:44.000000000 +0000
2540 CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400,
2541 CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4,
2542 CONFIG_SHANNON, CONFIG_P2_OMAP730, CONFIG_SMDK2400,
2543 - CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9
2544 + CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9,
2545 + CONFIG_AKITA, CONFIG_CORGI
2547 MicroBlaze based boards:
2548 ------------------------
2549 diff -Nur u-boot-2006-04-18-1106/board/akita/Makefile u-boot-2006-04-18-1106-new/board/akita/Makefile
2550 --- u-boot-2006-04-18-1106/board/akita/Makefile 1970-01-01 00:00:00.000000000 +0000
2551 +++ u-boot-2006-04-18-1106-new/board/akita/Makefile 2006-07-05 11:19:44.000000000 +0000
2554 +# board/akita/Makefile
2556 +# (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
2558 +# (C) Copyright 2000
2559 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
2561 +# See file CREDITS for list of people who contributed to this
2564 +# This program is free software; you can redistribute it and/or
2565 +# modify it under the terms of the GNU General Public License as
2566 +# published by the Free Software Foundation; either version 2 of
2567 +# the License, or (at your option) any later version.
2569 +# This program is distributed in the hope that it will be useful,
2570 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
2571 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2572 +# GNU General Public License for more details.
2574 +# You should have received a copy of the GNU General Public License
2575 +# along with this program; if not, write to the Free Software
2576 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2577 +# MA 02111-1307 USA
2580 +include $(TOPDIR)/config.mk
2582 +LIB = lib$(BOARD).a
2584 +OBJS := akita.o nand.o kbd.o
2585 +SOBJS := lowlevel_init.o
2587 +$(LIB): $(OBJS) $(SOBJS)
2588 + $(AR) crv $@ $(OBJS) $(SOBJS)
2591 + rm -f $(SOBJS) $(OBJS)
2594 + rm -f $(LIB) core *.bak .depend
2596 +#########################################################################
2598 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
2599 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
2603 +#########################################################################
2604 diff -Nur u-boot-2006-04-18-1106/board/akita/akita.c u-boot-2006-04-18-1106-new/board/akita/akita.c
2605 --- u-boot-2006-04-18-1106/board/akita/akita.c 1970-01-01 00:00:00.000000000 +0000
2606 +++ u-boot-2006-04-18-1106-new/board/akita/akita.c 2006-07-05 11:19:44.000000000 +0000
2609 + * board/akita/akita.c
2611 + * Configuration settings for the Sharp Zaurus SL-Cxx00.
2613 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
2615 + * portions from adsvix board configuration:
2616 + * (C) Copyright 2004
2617 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
2618 + * (C) Copyright 2002
2619 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
2620 + * (C) Copyright 2002
2621 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
2622 + * Marius Groeger <mgroeger@sysgo.de>
2624 + * See file CREDITS for list of people who contributed to this
2627 + * This program is free software; you can redistribute it and/or
2628 + * modify it under the terms of the GNU General Public License as
2629 + * published by the Free Software Foundation; either version 2 of
2630 + * the License, or (at your option) any later version.
2632 + * This program is distributed in the hope that it will be useful,
2633 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2634 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2635 + * GNU General Public License for more details.
2637 + * You should have received a copy of the GNU General Public License
2638 + * along with this program; if not, write to the Free Software
2639 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2640 + * MA 02111-1307 USA
2643 +#include <common.h>
2645 +void set_turbo_mode(void);
2647 +/* ------------------------------------------------------------------------- */
2650 + * Miscellaneous platform dependent initialisations
2653 +int board_init (void)
2655 + DECLARE_GLOBAL_DATA_PTR;
2657 + /* memory and cpu-speed are setup before relocation */
2658 + /* so we do _nothing_ here */
2660 + /* arch number of Sharp Zaurus Akita : MACH_TYPE_AKITA */
2661 + gd->bd->bi_arch_number = 744;
2663 + /* adress of boot parameters */
2664 + gd->bd->bi_boot_params = 0xa0000100;
2666 + /* set cpu turbo mode */
2674 +int board_late_init(void)
2676 + setenv("stdout", "serial");
2677 + setenv("stderr", "serial");
2682 +int dram_init (void)
2684 + DECLARE_GLOBAL_DATA_PTR;
2686 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
2687 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
2688 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
2689 + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
2690 + gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
2691 + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
2692 + gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
2693 + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
2697 diff -Nur u-boot-2006-04-18-1106/board/akita/config.mk u-boot-2006-04-18-1106-new/board/akita/config.mk
2698 --- u-boot-2006-04-18-1106/board/akita/config.mk 1970-01-01 00:00:00.000000000 +0000
2699 +++ u-boot-2006-04-18-1106-new/board/akita/config.mk 2006-07-05 11:19:44.000000000 +0000
2701 +TEXT_BASE = 0xa3000000
2702 diff -Nur u-boot-2006-04-18-1106/board/akita/kbd.c u-boot-2006-04-18-1106-new/board/akita/kbd.c
2703 --- u-boot-2006-04-18-1106/board/akita/kbd.c 1970-01-01 00:00:00.000000000 +0000
2704 +++ u-boot-2006-04-18-1106-new/board/akita/kbd.c 2006-07-05 11:19:44.000000000 +0000
2707 + * board/akita/kbd.c
2709 + * Keyboard driver for the Sharp Zaurus SL-Cxx00.
2711 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
2715 + * linux/drivers/input/keyboard/spitzkbd.c
2717 + * Keyboard driver for Sharp Spitz, Borzoi and Akita (SL-Cxx00 series)
2719 + * Copyright (C) 2005 Richard Purdie
2721 + * See file CREDITS for list of people who contributed to this
2724 + * This program is free software; you can redistribute it and/or
2725 + * modify it under the terms of the GNU General Public License as
2726 + * published by the Free Software Foundation; either version 2 of
2727 + * the License, or (at your option) any later version.
2729 + * This program is distributed in the hope that it will be useful,
2730 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2731 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2732 + * GNU General Public License for more details.
2734 + * You should have received a copy of the GNU General Public License
2735 + * along with this program; if not, write to the Free Software
2736 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2737 + * MA 02111-1307 USA
2740 +#include <common.h>
2741 +#include <command.h>
2742 +#include <config.h>
2743 +#include <version.h>
2744 +#include <asm/arch/pxa-regs.h>
2746 +#define GPIO_DFLT_LOW 0x400
2747 +#define GPIO_DFLT_HIGH 0x800
2749 +void pxa_gpio_mode(int gpio_mode)
2751 + int gpio = gpio_mode & GPIO_MD_MASK_NR;
2752 + int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
2755 + if (gpio_mode & GPIO_DFLT_LOW)
2756 + GPCR(gpio) = GPIO_bit(gpio);
2757 + else if (gpio_mode & GPIO_DFLT_HIGH)
2758 + GPSR(gpio) = GPIO_bit(gpio);
2759 + if (gpio_mode & GPIO_MD_MASK_DIR)
2760 + GPDR(gpio) |= GPIO_bit(gpio);
2762 + GPDR(gpio) &= ~GPIO_bit(gpio);
2763 + gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
2764 + GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
2767 +#define SPITZ_KEY_STROBE_NUM (11)
2768 +#define SPITZ_KEY_SENSE_NUM (7)
2770 +#define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000
2771 +#define SPITZ_GPIO_G1_STROBE_BIT 0x00100000
2772 +#define SPITZ_GPIO_G2_STROBE_BIT 0x01000000
2773 +#define SPITZ_GPIO_G3_STROBE_BIT 0x00041880
2774 +#define SPITZ_GPIO_G0_SENSE_BIT 0x00021000
2775 +#define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4
2776 +#define SPITZ_GPIO_G2_SENSE_BIT 0x08000000
2777 +#define SPITZ_GPIO_G3_SENSE_BIT 0x00000000
2779 +#define SPITZ_GPIO_KEY_STROBE0 88
2780 +#define SPITZ_GPIO_KEY_STROBE1 23
2781 +#define SPITZ_GPIO_KEY_STROBE2 24
2782 +#define SPITZ_GPIO_KEY_STROBE3 25
2783 +#define SPITZ_GPIO_KEY_STROBE4 26
2784 +#define SPITZ_GPIO_KEY_STROBE5 27
2785 +#define SPITZ_GPIO_KEY_STROBE6 52
2786 +#define SPITZ_GPIO_KEY_STROBE7 103
2787 +#define SPITZ_GPIO_KEY_STROBE8 107
2788 +#define SPITZ_GPIO_KEY_STROBE9 108
2789 +#define SPITZ_GPIO_KEY_STROBE10 114
2791 +#define SPITZ_GPIO_KEY_SENSE0 12
2792 +#define SPITZ_GPIO_KEY_SENSE1 17
2793 +#define SPITZ_GPIO_KEY_SENSE2 91
2794 +#define SPITZ_GPIO_KEY_SENSE3 34
2795 +#define SPITZ_GPIO_KEY_SENSE4 36
2796 +#define SPITZ_GPIO_KEY_SENSE5 38
2797 +#define SPITZ_GPIO_KEY_SENSE6 39
2799 +#define SPITZ_GPIO_ON_KEY (95)
2803 +#define KB_ROWMASK(r) (1 << (r))
2804 +#define SCANCODE(r,c) (((r)<<4) + (c) + 1)
2805 +#define NR_SCANCODES ((KB_ROWS<<4) + 1)
2807 +#define SCAN_INTERVAL (50) /* ms */
2808 +#define HINGE_SCAN_INTERVAL (150) /* ms */
2810 +#define KB_DISCHARGE_DELAY 10
2811 +#define KB_ACTIVATE_DELAY 10
2813 +static int spitz_strobes[] = {
2814 + SPITZ_GPIO_KEY_STROBE0,
2815 + SPITZ_GPIO_KEY_STROBE1,
2816 + SPITZ_GPIO_KEY_STROBE2,
2817 + SPITZ_GPIO_KEY_STROBE3,
2818 + SPITZ_GPIO_KEY_STROBE4,
2819 + SPITZ_GPIO_KEY_STROBE5,
2820 + SPITZ_GPIO_KEY_STROBE6,
2821 + SPITZ_GPIO_KEY_STROBE7,
2822 + SPITZ_GPIO_KEY_STROBE8,
2823 + SPITZ_GPIO_KEY_STROBE9,
2824 + SPITZ_GPIO_KEY_STROBE10,
2827 +static int spitz_senses[] = {
2828 + SPITZ_GPIO_KEY_SENSE0,
2829 + SPITZ_GPIO_KEY_SENSE1,
2830 + SPITZ_GPIO_KEY_SENSE2,
2831 + SPITZ_GPIO_KEY_SENSE3,
2832 + SPITZ_GPIO_KEY_SENSE4,
2833 + SPITZ_GPIO_KEY_SENSE5,
2834 + SPITZ_GPIO_KEY_SENSE6,
2837 +static inline void spitzkbd_discharge_all(void)
2839 + /* STROBE All HiZ */
2840 + GPCR0 = SPITZ_GPIO_G0_STROBE_BIT;
2841 + GPDR0 &= ~SPITZ_GPIO_G0_STROBE_BIT;
2842 + GPCR1 = SPITZ_GPIO_G1_STROBE_BIT;
2843 + GPDR1 &= ~SPITZ_GPIO_G1_STROBE_BIT;
2844 + GPCR2 = SPITZ_GPIO_G2_STROBE_BIT;
2845 + GPDR2 &= ~SPITZ_GPIO_G2_STROBE_BIT;
2846 + GPCR3 = SPITZ_GPIO_G3_STROBE_BIT;
2847 + GPDR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
2850 +static inline void spitzkbd_activate_all(void)
2852 + /* STROBE ALL -> High */
2853 + GPSR0 = SPITZ_GPIO_G0_STROBE_BIT;
2854 + GPDR0 |= SPITZ_GPIO_G0_STROBE_BIT;
2855 + GPSR1 = SPITZ_GPIO_G1_STROBE_BIT;
2856 + GPDR1 |= SPITZ_GPIO_G1_STROBE_BIT;
2857 + GPSR2 = SPITZ_GPIO_G2_STROBE_BIT;
2858 + GPDR2 |= SPITZ_GPIO_G2_STROBE_BIT;
2859 + GPSR3 = SPITZ_GPIO_G3_STROBE_BIT;
2860 + GPDR3 |= SPITZ_GPIO_G3_STROBE_BIT;
2862 + udelay(KB_DISCHARGE_DELAY);
2865 +static inline void spitzkbd_activate_col(int col)
2867 + int gpio = spitz_strobes[col];
2868 + GPDR0 &= ~SPITZ_GPIO_G0_STROBE_BIT;
2869 + GPDR1 &= ~SPITZ_GPIO_G1_STROBE_BIT;
2870 + GPDR2 &= ~SPITZ_GPIO_G2_STROBE_BIT;
2871 + GPDR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
2872 + GPSR(gpio) = GPIO_bit(gpio);
2873 + GPDR(gpio) |= GPIO_bit(gpio);
2876 +static inline void spitzkbd_reset_col(int col)
2878 + int gpio = spitz_strobes[col];
2879 + GPDR0 &= ~SPITZ_GPIO_G0_STROBE_BIT;
2880 + GPDR1 &= ~SPITZ_GPIO_G1_STROBE_BIT;
2881 + GPDR2 &= ~SPITZ_GPIO_G2_STROBE_BIT;
2882 + GPDR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
2883 + GPCR(gpio) = GPIO_bit(gpio);
2884 + GPDR(gpio) |= GPIO_bit(gpio);
2887 +static inline int spitzkbd_get_row_status(int col)
2889 + return ((GPLR0 >> 12) & 0x01) | ((GPLR0 >> 16) & 0x02)
2890 + | ((GPLR2 >> 25) & 0x04) | ((GPLR1 << 1) & 0x08)
2891 + | ((GPLR1 >> 0) & 0x10) | ((GPLR1 >> 1) & 0x60);
2894 +static int spitzkbd_scankeyboard(void)
2896 + unsigned int row, col, rowd;
2897 + unsigned int num_pressed, pwrkey = ((GPLR(SPITZ_GPIO_ON_KEY) & GPIO_bit(SPITZ_GPIO_ON_KEY)) != 0);
2901 + for (col = 0; col < KB_COLS; col++) {
2902 + spitzkbd_discharge_all();
2903 + udelay(KB_DISCHARGE_DELAY);
2905 + spitzkbd_activate_col(col);
2906 + udelay(KB_ACTIVATE_DELAY);
2908 + rowd = spitzkbd_get_row_status(col);
2909 + for (row = 0; row < KB_ROWS; row++) {
2910 + unsigned int scancode, pressed;
2912 + scancode = SCANCODE(row, col);
2913 + pressed = rowd & KB_ROWMASK(row);
2918 + spitzkbd_reset_col(col);
2921 + spitzkbd_activate_all();
2929 +void spitzkbd_init(void)
2933 + /* Setup sense interrupts - RisingEdge Detect, sense lines as inputs */
2934 + for (i = 0; i < SPITZ_KEY_SENSE_NUM; i++)
2935 + pxa_gpio_mode(spitz_senses[i] | GPIO_IN);
2937 + /* Set Strobe lines as outputs - set high */
2938 + for (i = 0; i < SPITZ_KEY_STROBE_NUM; i++)
2939 + pxa_gpio_mode(spitz_strobes[i] | GPIO_OUT | GPIO_DFLT_HIGH);
2941 + pxa_gpio_mode(SPITZ_GPIO_ON_KEY | GPIO_IN);
2944 +int do_testkey(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
2951 + scan = spitzkbd_scankeyboard();
2955 +// printf("Scan = %d\n", scan);
2957 +// printf("Nothing!\n");
2959 + return !(simple_strtol(argv[1], NULL, 10) == scan);
2963 + testkey, 2, 1, do_testkey,
2964 + "testkey - compare pressed key with arg\n",
2967 diff -Nur u-boot-2006-04-18-1106/board/akita/lowlevel_init.S u-boot-2006-04-18-1106-new/board/akita/lowlevel_init.S
2968 --- u-boot-2006-04-18-1106/board/akita/lowlevel_init.S 1970-01-01 00:00:00.000000000 +0000
2969 +++ u-boot-2006-04-18-1106-new/board/akita/lowlevel_init.S 2006-07-05 11:19:44.000000000 +0000
2972 + * board/akita/lowlevel_init.S
2974 + * Configuration settings for the Sharp Zaurus SL-Cxx00.
2976 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
2978 + * This was originally from the Lubbock u-boot port and from BLOB with cleanup
2980 + * NOTE: I haven't clean this up considerably, just enough to get it
2981 + * running. See hal_platform_setup.h for the source. See
2982 + * board/cradle/lowlevel_init.S for another PXA250 setup that is
2985 + * See file CREDITS for list of people who contributed to this
2988 + * This program is free software; you can redistribute it and/or
2989 + * modify it under the terms of the GNU General Public License as
2990 + * published by the Free Software Foundation; either version 2 of
2991 + * the License, or (at your option) any later version.
2993 + * This program is distributed in the hope that it will be useful,
2994 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2995 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2996 + * GNU General Public License for more details.
2998 + * You should have received a copy of the GNU General Public License
2999 + * along with this program; if not, write to the Free Software
3000 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3001 + * MA 02111-1307 USA
3004 +#include <config.h>
3005 +#include <version.h>
3006 +#include <asm/arch/pxa-regs.h>
3008 +/* wait for coprocessor write complete */
3010 + mrc p15,0,\reg,c2,c0,0
3015 +/*********** Write out to HEX 7 segment leds *********/
3017 +#undef DEBUG_HEXLOG
3019 +#ifdef DEBUG_HEXLOG
3020 +#define LEDCTL 0x08000040
3021 +#define LEDDAT1 0x08000010
3022 +#define LEDDAT2 0x08000014
3036 + mov r10, #0xFFFFFFFF
3048 + mov r10, #0xFFFFFFFF
3070 +/***********************************/
3076 +.globl lowlevel_init
3081 +.globl set_turbo_mode
3084 + /* Turn on turbo mode */
3085 + mrc p14, 0, r2, c6, c0, 0
3086 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
3087 + mcr p14, 0, r2, c6, c0, 0
3089 + /* Setup vectors */
3090 + ldr r0, =TEXT_BASE
3091 + ldr r1, =TEXT_BASE+0x40
3106 diff -Nur u-boot-2006-04-18-1106/board/akita/nand.c u-boot-2006-04-18-1106-new/board/akita/nand.c
3107 --- u-boot-2006-04-18-1106/board/akita/nand.c 1970-01-01 00:00:00.000000000 +0000
3108 +++ u-boot-2006-04-18-1106-new/board/akita/nand.c 2006-07-05 11:19:44.000000000 +0000
3111 + * board/akita/nand.c
3113 + * NAND driver for the Sharp Zaurus SL-Cxx00.
3115 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
3117 + * portions from mtd nand driver:
3119 + * drivers/mtd/nand/sharpsl.c
3121 + * Copyright (C) 2004 Richard Purdie
3123 + * See file CREDITS for list of people who contributed to this
3126 + * This program is free software; you can redistribute it and/or
3127 + * modify it under the terms of the GNU General Public License as
3128 + * published by the Free Software Foundation; either version 2 of
3129 + * the License, or (at your option) any later version.
3131 + * This program is distributed in the hope that it will be useful,
3132 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3133 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3134 + * GNU General Public License for more details.
3136 + * You should have received a copy of the GNU General Public License
3137 + * along with this program; if not, write to the Free Software
3138 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3139 + * MA 02111-1307 USA
3142 +#include <common.h>
3145 +#if (CONFIG_COMMANDS & CFG_CMD_NAND)
3148 +#include <linux/mtd/nand_ecc.h>
3150 +static int sharpsl_io_base = CFG_NAND_BASE;
3152 +/* register offset */
3153 +#define ECCLPLB sharpsl_io_base+0x00 /* line parity 7 - 0 bit */
3154 +#define ECCLPUB sharpsl_io_base+0x04 /* line parity 15 - 8 bit */
3155 +#define ECCCP sharpsl_io_base+0x08 /* column parity 5 - 0 bit */
3156 +#define ECCCNTR sharpsl_io_base+0x0C /* ECC byte counter */
3157 +#define ECCCLRR sharpsl_io_base+0x10 /* cleare ECC */
3158 +#define FLASHIO sharpsl_io_base+0x14 /* Flash I/O */
3159 +#define FLASHCTL sharpsl_io_base+0x18 /* Flash Control */
3161 +/* Flash control bit */
3162 +#define FLRYBY (1 << 5)
3163 +#define FLCE1 (1 << 4)
3164 +#define FLWP (1 << 3)
3165 +#define FLALE (1 << 2)
3166 +#define FLCLE (1 << 1)
3167 +#define FLCE0 (1 << 0)
3169 +#define readb(address) *((volatile unsigned char *)(address))
3170 +#define writeb(v, address) *((volatile unsigned char *)(address))=v
3173 + * hardware specific access to control-lines
3176 +sharpsl_nand_hwcontrol(struct mtd_info* mtd, int cmd)
3179 + case NAND_CTL_SETCLE:
3180 + writeb(readb(FLASHCTL) | FLCLE, FLASHCTL);
3182 + case NAND_CTL_CLRCLE:
3183 + writeb(readb(FLASHCTL) & ~FLCLE, FLASHCTL);
3186 + case NAND_CTL_SETALE:
3187 + writeb(readb(FLASHCTL) | FLALE, FLASHCTL);
3189 + case NAND_CTL_CLRALE:
3190 + writeb(readb(FLASHCTL) & ~FLALE, FLASHCTL);
3193 + case NAND_CTL_SETNCE:
3194 + writeb(readb(FLASHCTL) & ~(FLCE0|FLCE1), FLASHCTL);
3196 + case NAND_CTL_CLRNCE:
3197 + writeb(readb(FLASHCTL) | (FLCE0|FLCE1), FLASHCTL);
3203 +sharpsl_nand_dev_ready(struct mtd_info* mtd)
3205 + return !((readb(FLASHCTL) & FLRYBY) == 0);
3209 +sharpsl_nand_enable_hwecc(struct mtd_info* mtd, int mode)
3211 + writeb(0 ,ECCCLRR);
3215 +sharpsl_nand_calculate_ecc(struct mtd_info* mtd, const u_char* dat,
3218 + ecc_code[0] = ~readb(ECCLPUB);
3219 + ecc_code[1] = ~readb(ECCLPLB);
3220 + ecc_code[2] = (~readb(ECCCP) << 2) | 0x03;
3221 + return readb(ECCCNTR) != 0;
3224 +static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
3226 +static struct nand_bbt_descr sharpsl_akita_bbt = {
3230 + .pattern = scan_ff_pattern
3233 +static struct nand_oobinfo akita_oobinfo = {
3234 + .useecc = MTD_NANDECC_AUTOPLACE,
3237 + 0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
3238 + 0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
3239 + 0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
3240 + .oobfree = { {0x08, 0x09} }
3244 + * Board-specific NAND initialization. The following members of the
3245 + * argument are board-specific (per include/linux/mtd/nand.h):
3246 + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
3247 + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
3248 + * - hwcontrol: hardwarespecific function for accesing control-lines
3249 + * - dev_ready: hardwarespecific function for accesing device ready/busy line
3250 + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
3251 + * only be provided if a hardware ECC is available
3252 + * - eccmode: mode of ecc, see defines
3253 + * - chip_delay: chip dependent delay for transfering data from array to
3255 + * - options: various chip options. They can partly be set to inform
3256 + * nand_scan about special functionality. See the defines for further
3258 + * Members with a "?" were not set in the merged testing-NAND branch,
3259 + * so they are not set here either.
3261 +void board_nand_init(struct nand_chip *nand)
3263 + writeb(readb(FLASHCTL) | FLWP, FLASHCTL);
3265 + nand->IO_ADDR_R = FLASHIO;
3266 + nand->IO_ADDR_W = FLASHIO;
3267 + nand->hwcontrol = sharpsl_nand_hwcontrol;
3268 + nand->dev_ready = sharpsl_nand_dev_ready;
3269 + nand->eccmode = NAND_ECC_HW3_256;
3270 + nand->chip_delay = 15;
3271 + nand->options = NAND_SAMSUNG_LP_OPTIONS;
3272 + nand->badblock_pattern = &sharpsl_akita_bbt;
3273 + nand->autooob = &akita_oobinfo;
3274 + nand->enable_hwecc = sharpsl_nand_enable_hwecc;
3275 + nand->calculate_ecc = sharpsl_nand_calculate_ecc;
3276 + nand->correct_data = nand_correct_data;
3278 +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
3279 diff -Nur u-boot-2006-04-18-1106/board/akita/u-boot.lds u-boot-2006-04-18-1106-new/board/akita/u-boot.lds
3280 --- u-boot-2006-04-18-1106/board/akita/u-boot.lds 1970-01-01 00:00:00.000000000 +0000
3281 +++ u-boot-2006-04-18-1106-new/board/akita/u-boot.lds 2006-07-05 11:19:44.000000000 +0000
3284 + * (C) Copyright 2000
3285 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
3287 + * See file CREDITS for list of people who contributed to this
3290 + * This program is free software; you can redistribute it and/or
3291 + * modify it under the terms of the GNU General Public License as
3292 + * published by the Free Software Foundation; either version 2 of
3293 + * the License, or (at your option) any later version.
3295 + * This program is distributed in the hope that it will be useful,
3296 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3297 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3298 + * GNU General Public License for more details.
3300 + * You should have received a copy of the GNU General Public License
3301 + * along with this program; if not, write to the Free Software
3302 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3303 + * MA 02111-1307 USA
3306 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
3316 + cpu/pxa/start.o (.text)
3321 + .rodata : { *(.rodata) }
3324 + .data : { *(.data) }
3327 + .got : { *(.got) }
3330 + __u_boot_cmd_start = .;
3331 + .u_boot_cmd : { *(.u_boot_cmd) }
3332 + __u_boot_cmd_end = .;
3336 + .bss : { *(.bss) }
3339 diff -Nur u-boot-2006-04-18-1106/board/corgi/Makefile u-boot-2006-04-18-1106-new/board/corgi/Makefile
3340 --- u-boot-2006-04-18-1106/board/corgi/Makefile 1970-01-01 00:00:00.000000000 +0000
3341 +++ u-boot-2006-04-18-1106-new/board/corgi/Makefile 2006-07-05 11:19:44.000000000 +0000
3344 +# board/corgi/Makefile
3346 +# (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
3348 +# (C) Copyright 2000
3349 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
3351 +# See file CREDITS for list of people who contributed to this
3354 +# This program is free software; you can redistribute it and/or
3355 +# modify it under the terms of the GNU General Public License as
3356 +# published by the Free Software Foundation; either version 2 of
3357 +# the License, or (at your option) any later version.
3359 +# This program is distributed in the hope that it will be useful,
3360 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
3361 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3362 +# GNU General Public License for more details.
3364 +# You should have received a copy of the GNU General Public License
3365 +# along with this program; if not, write to the Free Software
3366 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3367 +# MA 02111-1307 USA
3370 +include $(TOPDIR)/config.mk
3372 +LIB = lib$(BOARD).a
3374 +OBJS := corgi.o nand.o kbd.o
3375 +SOBJS := lowlevel_init.o
3377 +$(LIB): $(OBJS) $(SOBJS)
3378 + $(AR) crv $@ $(OBJS) $(SOBJS)
3381 + rm -f $(SOBJS) $(OBJS)
3384 + rm -f $(LIB) core *.bak .depend
3386 +#########################################################################
3388 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
3389 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
3393 +#########################################################################
3394 diff -Nur u-boot-2006-04-18-1106/board/corgi/config.mk u-boot-2006-04-18-1106-new/board/corgi/config.mk
3395 --- u-boot-2006-04-18-1106/board/corgi/config.mk 1970-01-01 00:00:00.000000000 +0000
3396 +++ u-boot-2006-04-18-1106-new/board/corgi/config.mk 2006-07-05 11:19:44.000000000 +0000
3398 +TEXT_BASE = 0xa1000000
3399 diff -Nur u-boot-2006-04-18-1106/board/corgi/corgi.c u-boot-2006-04-18-1106-new/board/corgi/corgi.c
3400 --- u-boot-2006-04-18-1106/board/corgi/corgi.c 1970-01-01 00:00:00.000000000 +0000
3401 +++ u-boot-2006-04-18-1106-new/board/corgi/corgi.c 2006-07-05 11:19:44.000000000 +0000
3404 + * board/corgi/corgi.c
3406 + * Configuration settings for the Sharp Zaurus SL-C7x0/860.
3408 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
3410 + * portions from adsvix board configuration:
3411 + * (C) Copyright 2004
3412 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
3413 + * (C) Copyright 2002
3414 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
3415 + * (C) Copyright 2002
3416 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3417 + * Marius Groeger <mgroeger@sysgo.de>
3419 + * See file CREDITS for list of people who contributed to this
3422 + * This program is free software; you can redistribute it and/or
3423 + * modify it under the terms of the GNU General Public License as
3424 + * published by the Free Software Foundation; either version 2 of
3425 + * the License, or (at your option) any later version.
3427 + * This program is distributed in the hope that it will be useful,
3428 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3429 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3430 + * GNU General Public License for more details.
3432 + * You should have received a copy of the GNU General Public License
3433 + * along with this program; if not, write to the Free Software
3434 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3435 + * MA 02111-1307 USA
3438 +#include <common.h>
3440 +/* ------------------------------------------------------------------------- */
3443 + * Miscellaneous platform dependent initialisations
3446 +int board_init (void)
3448 + DECLARE_GLOBAL_DATA_PTR;
3450 + /* memory and cpu-speed are setup before relocation */
3451 + /* so we do _nothing_ here */
3453 + /* arch number of Sharp Zaurus Corgi : MACH_TYPE_CORGI */
3454 + gd->bd->bi_arch_number = 423;
3456 + /* adress of boot parameters */
3457 + gd->bd->bi_boot_params = 0xa0000100;
3459 + /* set cpu turbo mode */
3467 +int board_late_init(void)
3469 + setenv("stdout", "serial");
3470 + setenv("stderr", "serial");
3475 +int dram_init (void)
3477 + DECLARE_GLOBAL_DATA_PTR;
3479 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
3480 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
3481 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
3482 + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
3483 + gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
3484 + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
3485 + gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
3486 + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
3490 diff -Nur u-boot-2006-04-18-1106/board/corgi/kbd.c u-boot-2006-04-18-1106-new/board/corgi/kbd.c
3491 --- u-boot-2006-04-18-1106/board/corgi/kbd.c 1970-01-01 00:00:00.000000000 +0000
3492 +++ u-boot-2006-04-18-1106-new/board/corgi/kbd.c 2006-07-05 11:19:44.000000000 +0000
3495 + * board/corgi/kbd.c
3497 + * Keyboard driver for the Sharp Zaurus SL-C7x0/860.
3499 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
3503 + * linux/drivers/input/keyboard/spitzkbd.c
3505 + * Keyboard driver for Sharp Corgi models (SL-C7xx)
3507 + * Copyright (C) 2005 Richard Purdie
3509 + * See file CREDITS for list of people who contributed to this
3512 + * This program is free software; you can redistribute it and/or
3513 + * modify it under the terms of the GNU General Public License as
3514 + * published by the Free Software Foundation; either version 2 of
3515 + * the License, or (at your option) any later version.
3517 + * This program is distributed in the hope that it will be useful,
3518 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3519 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3520 + * GNU General Public License for more details.
3522 + * You should have received a copy of the GNU General Public License
3523 + * along with this program; if not, write to the Free Software
3524 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3525 + * MA 02111-1307 USA
3528 +#include <common.h>
3529 +#include <command.h>
3530 +#include <config.h>
3531 +#include <version.h>
3532 +#include <asm/arch/pxa-regs.h>
3534 +#define GPIO_DFLT_LOW 0x400
3535 +#define GPIO_DFLT_HIGH 0x800
3537 +void pxa_gpio_mode(int gpio_mode)
3539 + int gpio = gpio_mode & GPIO_MD_MASK_NR;
3540 + int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
3543 + if (gpio_mode & GPIO_DFLT_LOW)
3544 + GPCR(gpio) = GPIO_bit(gpio);
3545 + else if (gpio_mode & GPIO_DFLT_HIGH)
3546 + GPSR(gpio) = GPIO_bit(gpio);
3547 + if (gpio_mode & GPIO_MD_MASK_DIR)
3548 + GPDR(gpio) |= GPIO_bit(gpio);
3550 + GPDR(gpio) &= ~GPIO_bit(gpio);
3551 + gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
3552 + GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
3556 + * Corgi Keyboard Definitions
3558 +#define CORGI_KEY_STROBE_NUM (12)
3559 +#define CORGI_KEY_SENSE_NUM (8)
3560 +#define CORGI_GPIO_ALL_STROBE_BIT (0x00003ffc)
3561 +#define CORGI_GPIO_HIGH_SENSE_BIT (0xfc000000)
3562 +#define CORGI_GPIO_HIGH_SENSE_RSHIFT (26)
3563 +#define CORGI_GPIO_LOW_SENSE_BIT (0x00000003)
3564 +#define CORGI_GPIO_LOW_SENSE_LSHIFT (6)
3565 +#define CORGI_GPIO_STROBE_BIT(a) GPIO_bit(66+(a))
3566 +#define CORGI_GPIO_SENSE_BIT(a) GPIO_bit(58+(a))
3567 +#define CORGI_GAFR_ALL_STROBE_BIT (0x0ffffff0)
3568 +#define CORGI_GAFR_HIGH_SENSE_BIT (0xfff00000)
3569 +#define CORGI_GAFR_LOW_SENSE_BIT (0x0000000f)
3570 +#define CORGI_GPIO_KEY_SENSE(a) (58+(a))
3571 +#define CORGI_GPIO_KEY_STROBE(a) (66+(a))
3573 +#define CORGI_GPIO_AK_INT (4) /* Headphone Jack Control Interrupt */
3577 +#define KB_ROWMASK(r) (1 << (r))
3578 +#define SCANCODE(r,c) ( ((r)<<4) + (c) + 1 )
3579 +/* zero code, 124 scancodes */
3580 +#define NR_SCANCODES ( SCANCODE(KB_ROWS-1,KB_COLS-1) +1 +1 )
3582 +#define SCAN_INTERVAL (50) /* ms */
3583 +#define HINGE_SCAN_INTERVAL (250) /* ms */
3585 +#define KB_DISCHARGE_DELAY 10
3586 +#define KB_ACTIVATE_DELAY 10
3588 +static inline void corgikbd_discharge_all(void)
3590 + /* STROBE All HiZ */
3591 + GPCR2 = CORGI_GPIO_ALL_STROBE_BIT;
3592 + GPDR2 &= ~CORGI_GPIO_ALL_STROBE_BIT;
3595 +static inline void corgikbd_activate_all(void)
3597 + /* STROBE ALL -> High */
3598 + GPSR2 = CORGI_GPIO_ALL_STROBE_BIT;
3599 + GPDR2 |= CORGI_GPIO_ALL_STROBE_BIT;
3601 + udelay(KB_DISCHARGE_DELAY);
3603 + /* Clear any interrupts we may have triggered when altering the GPIO lines */
3604 + GEDR1 = CORGI_GPIO_HIGH_SENSE_BIT;
3605 + GEDR2 = CORGI_GPIO_LOW_SENSE_BIT;
3608 +static inline void corgikbd_activate_col(int col)
3610 + /* STROBE col -> High, not col -> HiZ */
3611 + GPSR2 = CORGI_GPIO_STROBE_BIT(col);
3612 + GPDR2 = (GPDR2 & ~CORGI_GPIO_ALL_STROBE_BIT) | CORGI_GPIO_STROBE_BIT(col);
3615 +static inline void corgikbd_reset_col(int col)
3617 + /* STROBE col -> Low */
3618 + GPCR2 = CORGI_GPIO_STROBE_BIT(col);
3619 + /* STROBE col -> out, not col -> HiZ */
3620 + GPDR2 = (GPDR2 & ~CORGI_GPIO_ALL_STROBE_BIT) | CORGI_GPIO_STROBE_BIT(col);
3623 +#define GET_ROWS_STATUS(c) (((GPLR1 & CORGI_GPIO_HIGH_SENSE_BIT) >> CORGI_GPIO_HIGH_SENSE_RSHIFT) | ((GPLR2 & CORGI_GPIO_LOW_SENSE_BIT) << CORGI_GPIO_LOW_SENSE_LSHIFT))
3625 +static int corgikbd_scankeyboard(void)
3627 + unsigned int row, col, rowd;
3628 + unsigned int num_pressed;
3632 + for (col = 0; col < KB_COLS; col++) {
3633 + corgikbd_discharge_all();
3634 + udelay(KB_DISCHARGE_DELAY);
3636 + corgikbd_activate_col(col);
3637 + udelay(KB_ACTIVATE_DELAY);
3639 + rowd = GET_ROWS_STATUS(col);
3640 + for (row = 0; row < KB_ROWS; row++) {
3641 + unsigned int scancode, pressed;
3643 + scancode = SCANCODE(row, col);
3644 + pressed = rowd & KB_ROWMASK(row);
3649 + corgikbd_reset_col(col);
3652 + corgikbd_activate_all();
3657 +void corgikbd_init(void)
3661 + /* Setup sense interrupts - RisingEdge Detect, sense lines as inputs */
3662 + for (i = 0; i < CORGI_KEY_SENSE_NUM; i++)
3663 + pxa_gpio_mode(CORGI_GPIO_KEY_SENSE(i) | GPIO_IN);
3665 + /* Set Strobe lines as outputs - set high */
3666 + for (i = 0; i < CORGI_KEY_STROBE_NUM; i++)
3667 + pxa_gpio_mode(CORGI_GPIO_KEY_STROBE(i) | GPIO_OUT | GPIO_DFLT_HIGH);
3669 + /* Setup the headphone jack as an input */
3670 + pxa_gpio_mode(CORGI_GPIO_AK_INT | GPIO_IN);
3673 +int do_testkey(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3680 + scan = corgikbd_scankeyboard();
3684 +// printf("Scan = %d\n", scan);
3686 +// printf("Nothing!\n");
3688 + return !(simple_strtol(argv[1], NULL, 10) == scan);
3692 + testkey, 2, 1, do_testkey,
3693 + "testkey - compare pressed key with arg\n",
3696 diff -Nur u-boot-2006-04-18-1106/board/corgi/lowlevel_init.S u-boot-2006-04-18-1106-new/board/corgi/lowlevel_init.S
3697 --- u-boot-2006-04-18-1106/board/corgi/lowlevel_init.S 1970-01-01 00:00:00.000000000 +0000
3698 +++ u-boot-2006-04-18-1106-new/board/corgi/lowlevel_init.S 2006-07-05 11:19:44.000000000 +0000
3701 + * board/corgi/lowlevel_init.S
3703 + * Configuration settings for the Sharp Zaurus SL-C7x0/860.
3705 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
3707 + * This was originally from the Lubbock u-boot port and from BLOB with cleanup
3709 + * NOTE: I haven't clean this up considerably, just enough to get it
3710 + * running. See hal_platform_setup.h for the source. See
3711 + * board/cradle/lowlevel_init.S for another PXA250 setup that is
3714 + * See file CREDITS for list of people who contributed to this
3717 + * This program is free software; you can redistribute it and/or
3718 + * modify it under the terms of the GNU General Public License as
3719 + * published by the Free Software Foundation; either version 2 of
3720 + * the License, or (at your option) any later version.
3722 + * This program is distributed in the hope that it will be useful,
3723 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3724 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3725 + * GNU General Public License for more details.
3727 + * You should have received a copy of the GNU General Public License
3728 + * along with this program; if not, write to the Free Software
3729 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3730 + * MA 02111-1307 USA
3733 +#include <config.h>
3734 +#include <version.h>
3735 +#include <asm/arch/pxa-regs.h>
3737 +/* wait for coprocessor write complete */
3739 + mrc p15,0,\reg,c2,c0,0
3744 +/*********** Write out to HEX 7 segment leds *********/
3746 +#undef DEBUG_HEXLOG
3748 +#ifdef DEBUG_HEXLOG
3749 +#define LEDCTL 0x08000040
3750 +#define LEDDAT1 0x08000010
3751 +#define LEDDAT2 0x08000014
3765 + mov r10, #0xFFFFFFFF
3777 + mov r10, #0xFFFFFFFF
3799 +/***********************************/
3805 +.globl lowlevel_init
3810 +.globl set_turbo_mode
3813 + /* Turn on turbo mode */
3814 + mrc p14, 0, r2, c6, c0, 0
3815 + orr r2, r2, #0x3 /* Turbo, Freq change */
3816 + mcr p14, 0, r2, c6, c0, 0
3819 + /* Setup vectors */
3820 + ldr r0, =TEXT_BASE
3821 + ldr r1, =TEXT_BASE+0x40
3836 diff -Nur u-boot-2006-04-18-1106/board/corgi/nand.c u-boot-2006-04-18-1106-new/board/corgi/nand.c
3837 --- u-boot-2006-04-18-1106/board/corgi/nand.c 1970-01-01 00:00:00.000000000 +0000
3838 +++ u-boot-2006-04-18-1106-new/board/corgi/nand.c 2006-07-05 11:19:44.000000000 +0000
3841 + * board/corgi/nand.c
3843 + * NAND driver for the Sharp Zaurus SL-C7x0/860.
3845 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
3847 + * portions from mtd nand driver:
3849 + * drivers/mtd/nand/sharpsl.c
3851 + * Copyright (C) 2004 Richard Purdie
3853 + * See file CREDITS for list of people who contributed to this
3856 + * This program is free software; you can redistribute it and/or
3857 + * modify it under the terms of the GNU General Public License as
3858 + * published by the Free Software Foundation; either version 2 of
3859 + * the License, or (at your option) any later version.
3861 + * This program is distributed in the hope that it will be useful,
3862 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3863 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3864 + * GNU General Public License for more details.
3866 + * You should have received a copy of the GNU General Public License
3867 + * along with this program; if not, write to the Free Software
3868 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3869 + * MA 02111-1307 USA
3872 +#include <common.h>
3875 +#if (CONFIG_COMMANDS & CFG_CMD_NAND)
3878 +#include <linux/mtd/nand_ecc.h>
3880 +static int sharpsl_io_base = CFG_NAND_BASE;
3882 +/* register offset */
3883 +#define ECCLPLB sharpsl_io_base+0x00 /* line parity 7 - 0 bit */
3884 +#define ECCLPUB sharpsl_io_base+0x04 /* line parity 15 - 8 bit */
3885 +#define ECCCP sharpsl_io_base+0x08 /* column parity 5 - 0 bit */
3886 +#define ECCCNTR sharpsl_io_base+0x0C /* ECC byte counter */
3887 +#define ECCCLRR sharpsl_io_base+0x10 /* cleare ECC */
3888 +#define FLASHIO sharpsl_io_base+0x14 /* Flash I/O */
3889 +#define FLASHCTL sharpsl_io_base+0x18 /* Flash Control */
3891 +/* Flash control bit */
3892 +#define FLRYBY (1 << 5)
3893 +#define FLCE1 (1 << 4)
3894 +#define FLWP (1 << 3)
3895 +#define FLALE (1 << 2)
3896 +#define FLCLE (1 << 1)
3897 +#define FLCE0 (1 << 0)
3899 +#define readb(address) *((volatile unsigned char *)(address))
3900 +#define writeb(v, address) *((volatile unsigned char *)(address))=v
3903 + * hardware specific access to control-lines
3906 +sharpsl_nand_hwcontrol(struct mtd_info* mtd, int cmd)
3909 + case NAND_CTL_SETCLE:
3910 + writeb(readb(FLASHCTL) | FLCLE, FLASHCTL);
3912 + case NAND_CTL_CLRCLE:
3913 + writeb(readb(FLASHCTL) & ~FLCLE, FLASHCTL);
3916 + case NAND_CTL_SETALE:
3917 + writeb(readb(FLASHCTL) | FLALE, FLASHCTL);
3919 + case NAND_CTL_CLRALE:
3920 + writeb(readb(FLASHCTL) & ~FLALE, FLASHCTL);
3923 + case NAND_CTL_SETNCE:
3924 + writeb(readb(FLASHCTL) & ~(FLCE0|FLCE1), FLASHCTL);
3926 + case NAND_CTL_CLRNCE:
3927 + writeb(readb(FLASHCTL) | (FLCE0|FLCE1), FLASHCTL);
3933 +sharpsl_nand_dev_ready(struct mtd_info* mtd)
3935 + return !((readb(FLASHCTL) & FLRYBY) == 0);
3939 +sharpsl_nand_enable_hwecc(struct mtd_info* mtd, int mode)
3941 + writeb(0 ,ECCCLRR);
3945 +sharpsl_nand_calculate_ecc(struct mtd_info* mtd, const u_char* dat,
3948 + ecc_code[0] = ~readb(ECCLPUB);
3949 + ecc_code[1] = ~readb(ECCLPLB);
3950 + ecc_code[2] = (~readb(ECCCP) << 2) | 0x03;
3951 + return readb(ECCCNTR) != 0;
3954 +static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
3956 +static struct nand_bbt_descr sharpsl_bbt = {
3960 + .pattern = scan_ff_pattern
3964 + * Board-specific NAND initialization. The following members of the
3965 + * argument are board-specific (per include/linux/mtd/nand.h):
3966 + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
3967 + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
3968 + * - hwcontrol: hardwarespecific function for accesing control-lines
3969 + * - dev_ready: hardwarespecific function for accesing device ready/busy line
3970 + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
3971 + * only be provided if a hardware ECC is available
3972 + * - eccmode: mode of ecc, see defines
3973 + * - chip_delay: chip dependent delay for transfering data from array to
3975 + * - options: various chip options. They can partly be set to inform
3976 + * nand_scan about special functionality. See the defines for further
3978 + * Members with a "?" were not set in the merged testing-NAND branch,
3979 + * so they are not set here either.
3981 +void board_nand_init(struct nand_chip *nand)
3983 + writeb(readb(FLASHCTL) | FLWP, FLASHCTL);
3985 + nand->IO_ADDR_R = FLASHIO;
3986 + nand->IO_ADDR_W = FLASHIO;
3987 + nand->hwcontrol = sharpsl_nand_hwcontrol;
3988 + nand->dev_ready = sharpsl_nand_dev_ready;
3989 + nand->eccmode = NAND_ECC_HW3_256;
3990 + nand->chip_delay = 15;
3991 + nand->badblock_pattern = &sharpsl_bbt;
3992 + nand->enable_hwecc = sharpsl_nand_enable_hwecc;
3993 + nand->calculate_ecc = sharpsl_nand_calculate_ecc;
3994 + nand->correct_data = nand_correct_data;
3996 +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
3997 diff -Nur u-boot-2006-04-18-1106/board/corgi/u-boot.lds u-boot-2006-04-18-1106-new/board/corgi/u-boot.lds
3998 --- u-boot-2006-04-18-1106/board/corgi/u-boot.lds 1970-01-01 00:00:00.000000000 +0000
3999 +++ u-boot-2006-04-18-1106-new/board/corgi/u-boot.lds 2006-07-05 11:19:44.000000000 +0000
4002 + * (C) Copyright 2000
4003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4005 + * See file CREDITS for list of people who contributed to this
4008 + * This program is free software; you can redistribute it and/or
4009 + * modify it under the terms of the GNU General Public License as
4010 + * published by the Free Software Foundation; either version 2 of
4011 + * the License, or (at your option) any later version.
4013 + * This program is distributed in the hope that it will be useful,
4014 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4015 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4016 + * GNU General Public License for more details.
4018 + * You should have received a copy of the GNU General Public License
4019 + * along with this program; if not, write to the Free Software
4020 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4021 + * MA 02111-1307 USA
4024 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
4034 + cpu/pxa/start.o (.text)
4039 + .rodata : { *(.rodata) }
4042 + .data : { *(.data) }
4045 + .got : { *(.got) }
4048 + __u_boot_cmd_start = .;
4049 + .u_boot_cmd : { *(.u_boot_cmd) }
4050 + __u_boot_cmd_end = .;
4054 + .bss : { *(.bss) }
4057 diff -Nur u-boot-2006-04-18-1106/common/cmd_nand.c u-boot-2006-04-18-1106-new/common/cmd_nand.c
4058 --- u-boot-2006-04-18-1106/common/cmd_nand.c 2006-04-18 09:05:03.000000000 +0000
4059 +++ u-boot-2006-04-18-1106-new/common/cmd_nand.c 2006-07-05 11:19:44.000000000 +0000
4064 +#ifdef NAND_LOGICAL
4065 +/////////////////////////////////////////////////////////////////////
4067 +/////////////////////////////////////////////////////////////////////
4069 +#define NAND_NOOB_LOGADDR_00 8
4070 +#define NAND_NOOB_LOGADDR_01 9
4071 +#define NAND_NOOB_LOGADDR_10 10
4072 +#define NAND_NOOB_LOGADDR_11 11
4073 +#define NAND_NOOB_LOGADDR_20 12
4074 +#define NAND_NOOB_LOGADDR_21 13
4076 +static uint nand_get_logical_no(unsigned char *oob)
4078 + unsigned short us,bit;
4082 + if(oob[NAND_NOOB_LOGADDR_00] == oob[NAND_NOOB_LOGADDR_10] &&
4083 + oob[NAND_NOOB_LOGADDR_01] == oob[NAND_NOOB_LOGADDR_11]){
4084 + good0 = NAND_NOOB_LOGADDR_00;
4085 + good1 = NAND_NOOB_LOGADDR_01;
4087 + if(oob[NAND_NOOB_LOGADDR_10] == oob[NAND_NOOB_LOGADDR_20] &&
4088 + oob[NAND_NOOB_LOGADDR_11] == oob[NAND_NOOB_LOGADDR_21]){
4089 + good0 = NAND_NOOB_LOGADDR_10;
4090 + good1 = NAND_NOOB_LOGADDR_11;
4092 + if(oob[NAND_NOOB_LOGADDR_20] == oob[NAND_NOOB_LOGADDR_00] &&
4093 + oob[NAND_NOOB_LOGADDR_21] == oob[NAND_NOOB_LOGADDR_01]){
4094 + good0 = NAND_NOOB_LOGADDR_20;
4095 + good1 = NAND_NOOB_LOGADDR_21;
4100 + us = (((unsigned short)(oob[good0]) & 0x00ff) << 0) |
4101 + (((unsigned short)(oob[good1]) & 0x00ff) << 8);
4104 + for(bit = 0x0001; bit != 0; bit <<= 1){
4116 + return ((us & 0x07fe) >> 1);
4121 /* ------------------------------------------------------------------------- */
4124 @@ -245,6 +302,55 @@
4125 if (off == 0 && size == 0)
4128 +#ifdef NAND_LOGICAL
4129 + s = strchr(cmd, '.');
4131 + if (strcmp(s, ".logical") == 0) {
4132 + int blocks = NAND_LOGICAL_SIZE / nand->erasesize;
4133 + ulong *log2phy = malloc(blocks * sizeof(ulong));
4134 + u_char *oobuf = malloc(nand->oobblock + nand->oobsize);
4138 + for (i = 0; i < blocks; i++)
4139 + log2phy[i] = (uint) -1;
4141 + for (i = 0; i < blocks; i++) {
4142 + ret = nand_read_raw(nand, oobuf, offset, nand->oobblock, nand->oobsize);
4144 + int log_no = nand_get_logical_no(oobuf + nand->oobblock);
4145 + if (((int)log_no >= 0) && (log_no < blocks)) {
4146 + log2phy[log_no] = offset;
4147 + //printf("NAND logical - %08X -> %04X\n", offset, log_no);
4150 + offset += nand->erasesize;
4153 + for (i = 0; i < size / nand->erasesize; i++) {
4154 + ulong sz = nand->erasesize;
4155 + offset = log2phy[off / nand->erasesize];
4156 + if ((int)offset < 0) {
4157 + printf("NAND logical - offset %08X not found\n", off);
4160 + //printf("NAND logical - %04X -> %08X\n", off / nand->erasesize, offset);
4161 + ret = nand_read(nand, offset, &sz, (u_char *)addr);
4163 + printf("NAND logical - offset %08X, read error\n", off);
4166 + off += nand->erasesize;
4167 + addr += nand->erasesize;
4169 + printf(" %d bytes read from NAND logical\n", size);
4172 + return ret == 0 ? 0 : 1;
4177 i = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
4178 printf("\nNAND %s: device %d offset %u, size %u ... ",
4179 i ? "read" : "write", nand_curr_device, off, size);
4180 diff -Nur u-boot-2006-04-18-1106/cpu/pxa/config.mk u-boot-2006-04-18-1106-new/cpu/pxa/config.mk
4181 --- u-boot-2006-04-18-1106/cpu/pxa/config.mk 2006-04-18 09:05:03.000000000 +0000
4182 +++ u-boot-2006-04-18-1106-new/cpu/pxa/config.mk 2006-07-05 11:19:44.000000000 +0000
4187 -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
4189 +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 -fomit-frame-pointer
4191 #PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
4192 PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale
4194 # Supply options according to compiler version
4196 # ========================================================================
4197 -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
4198 +#PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
4199 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
4200 diff -Nur u-boot-2006-04-18-1106/cpu/pxa/start.S u-boot-2006-04-18-1106-new/cpu/pxa/start.S
4201 --- u-boot-2006-04-18-1106/cpu/pxa/start.S 2006-04-18 09:05:03.000000000 +0000
4202 +++ u-boot-2006-04-18-1106-new/cpu/pxa/start.S 2006-07-05 11:19:44.000000000 +0000
4207 +_reset: .word reset
4208 _undefined_instruction: .word undefined_instruction
4209 _software_interrupt: .word software_interrupt
4210 _prefetch_abort: .word prefetch_abort
4211 diff -Nur u-boot-2006-04-18-1106/fs/cramfs/cramfs.c u-boot-2006-04-18-1106-new/fs/cramfs/cramfs.c
4212 --- u-boot-2006-04-18-1106/fs/cramfs/cramfs.c 2006-04-18 09:05:03.000000000 +0000
4213 +++ u-boot-2006-04-18-1106-new/fs/cramfs/cramfs.c 2006-07-05 11:19:44.000000000 +0000
4216 /* CPU address space offset calculation macro, struct part_info offset is
4217 * device address space offset, so we need to shift it by a device start address. */
4218 +#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
4219 extern flash_info_t flash_info[];
4220 #define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0])
4222 +static struct cramfs_super super_fake;
4223 +#define PART_OFFSET(x) (&super_fake)
4226 static int cramfs_read_super (struct part_info *info)
4228 diff -Nur u-boot-2006-04-18-1106/include/asm-arm/arch-pxa/pxa-regs.h u-boot-2006-04-18-1106-new/include/asm-arm/arch-pxa/pxa-regs.h
4229 --- u-boot-2006-04-18-1106/include/asm-arm/arch-pxa/pxa-regs.h 2006-04-18 09:05:03.000000000 +0000
4230 +++ u-boot-2006-04-18-1106-new/include/asm-arm/arch-pxa/pxa-regs.h 2006-07-05 11:19:44.000000000 +0000
4231 @@ -1269,15 +1269,16 @@
4232 #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
4233 #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
4235 -#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
4236 -#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
4237 -#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
4238 -#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
4239 -#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
4240 -#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
4241 -#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
4242 -#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \
4243 - ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
4244 +#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
4245 +#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
4246 +#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
4247 +#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
4248 +#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
4249 +#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
4250 +#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
4251 +#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
4252 + ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
4256 #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
4257 diff -Nur u-boot-2006-04-18-1106/include/configs/akita.h u-boot-2006-04-18-1106-new/include/configs/akita.h
4258 --- u-boot-2006-04-18-1106/include/configs/akita.h 1970-01-01 00:00:00.000000000 +0000
4259 +++ u-boot-2006-04-18-1106-new/include/configs/akita.h 2006-07-13 11:00:46.000000000 +0000
4262 + * include/configs/akita.h
4264 + * Configuration settings for the Sharp Zaurus SL-C1000/C3100.
4266 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
4268 + * portions from adsvix board configuration:
4269 + * (C) Copyright 2004
4270 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
4271 + * (C) Copyright 2002
4272 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4273 + * (C) Copyright 2002
4274 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4275 + * Marius Groeger <mgroeger@sysgo.de>
4277 + * See file CREDITS for list of people who contributed to this
4280 + * This program is free software; you can redistribute it and/or
4281 + * modify it under the terms of the GNU General Public License as
4282 + * published by the Free Software Foundation; either version 2 of
4283 + * the License, or (at your option) any later version.
4285 + * This program is distributed in the hope that it will be useful,
4286 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4287 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4288 + * GNU General Public License for more details.
4290 + * You should have received a copy of the GNU General Public License
4291 + * along with this program; if not, write to the Free Software
4292 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4293 + * MA 02111-1307 USA
4299 +#define CONFIG_SKIP_LOWLEVEL_INIT
4301 +#undef SKIP_CONFIG_RELOCATE_UBOOT
4303 +#undef CONFIG_HARD_I2C
4306 + * High Level Configuration Options
4307 + * (easy to change)
4309 +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
4310 +#define CONFIG_AKITA 1 /* on Sharp Zaurus Akita */
4311 +//#define CONFIG_MMC 1
4312 +#define BOARD_LATE_INIT 1
4314 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
4319 + * Size of malloc() pool
4321 +//#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
4322 +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
4323 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
4326 + * select serial console configuration
4328 +#define CONFIG_FFUART 1 /* we use FFUART on Mainstone */
4330 +/* allow to overwrite serial and ethaddr */
4331 +#define CONFIG_BAUDRATE 115200
4332 +//#define CONFIG_DOS_PARTITION 1
4334 +#undef CONFIG_SHOW_BOOT_PROGRESS
4337 +#define CONFIG_BOOTDELAY 1
4338 +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n"
4340 +#define CONFIG_BOOTCOMMAND \
4341 + "if testkey 101 ; " \
4343 + "nand read.logical 0xa1000000 0x00060000 0x00540000; " \
4344 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/ram rw fbcon=rotate:1 ramdisk_size=8192; " \
4347 + "if testkey 2 ; " \
4349 + "nand read.logical 0xa1000000 0x005a0000 0x00160000; " \
4350 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/mmcblk0p1 fbcon=rotate:1; " \
4353 + "if testkey 18 ; " \
4355 + "nand read.logical 0xa1000000 0x005a0000 0x00160000; " \
4356 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/hda1 fbcon=rotate:1; " \
4359 + "if testkey 3 ; " \
4361 + "nand read.logical 0xa1000000 0x005a0000 0x00160000; " \
4362 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/hdc1 fbcon=rotate:1; " \
4365 + "nand read.logical 0xa1000000 0x005a0000 0x00160000; " \
4366 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/mtdblock2 rootfstype=jffs2 fbcon=rotate:1; " \
4369 +#define CONFIG_BOOTCOMMAND "" // "run boot_flash"
4372 +#define CONFIG_BOOTARGS "console=ttyS0,115200 console=tty1 root=/dev/ram rw fbcon=rotate:1 ramdisk_size=8192"
4373 +#define CONFIG_SETUP_MEMORY_TAGS 1
4374 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
4375 +#define CONFIG_INITRD_TAG 1
4377 +#define CONFIG_COMMANDS (( \
4378 + CONFIG_CMD_DFL | \
4389 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
4390 +#include <cmd_confdefs.h>
4393 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
4394 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
4395 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
4399 + * Miscellaneous configurable options
4401 +#define CFG_HUSH_PARSER 1
4402 +#define CFG_PROMPT_HUSH_PS2 "> "
4404 +#define CFG_LONGHELP /* undef to save memory */
4405 +#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
4407 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
4408 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
4409 +#define CFG_MAXARGS 16 /* max number of command args */
4410 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
4411 +#define CFG_DEVICE_NULLDEV 1
4413 +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
4414 +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
4416 +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
4418 +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */
4420 +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
4421 +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
4423 + /* valid baudrates */
4424 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
4426 +#define CFG_MMC_BASE 0xF0000000
4431 + * The stack sizes are set up in start.S using the settings below
4433 +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
4434 +#ifdef CONFIG_USE_IRQ
4435 +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
4436 +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
4440 + * Physical Memory Map
4442 +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
4443 +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
4444 +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
4445 +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
4446 +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
4447 +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
4448 +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
4449 +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
4450 +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
4452 +#define PHYS_FLASH_1 0xd4000000 /* Flash Bank #1 */
4454 +#define CFG_DRAM_BASE 0xa0000000
4455 +#define CFG_DRAM_SIZE 0x04000000
4457 +#define CFG_FLASH_BASE PHYS_FLASH_1
4460 + * GPIO settings for Mainstone
4463 +#define CFG_GPSR0_VAL 0x00708800
4464 +#define CFG_GPSR1_VAL 0x03cf0002
4465 +#define CFG_GPSR2_VAL 0x0021FC00
4466 +#define CFG_GPSR3_VAL 0x00000000
4468 +#define CFG_GPCR0_VAL 0x00001000
4469 +#define CFG_GPCR1_VAL 0x00000000
4470 +#define CFG_GPCR2_VAL 0x00000000
4471 +#define CFG_GPCR3_VAL 0x00000000
4473 +#define CFG_GPDR0_VAL 0xC27B9C04
4474 +#define CFG_GPDR1_VAL 0x00EFAA83
4475 +#define CFG_GPDR2_VAL 0x0E23FC00
4476 +#define CFG_GPDR3_VAL 0x001E1F81
4478 +#define CFG_GAFR0_L_VAL 0x94F00000
4479 +#define CFG_GAFR0_U_VAL 0x015A859A
4480 +#define CFG_GAFR1_L_VAL 0x999A955A
4481 +#define CFG_GAFR1_U_VAL 0x0005A4AA
4482 +#define CFG_GAFR2_L_VAL 0x6AA00000
4483 +#define CFG_GAFR2_U_VAL 0x55A8041A
4484 +#define CFG_GAFR3_L_VAL 0x56AA955A
4485 +#define CFG_GAFR3_U_VAL 0x00000001
4487 +#define CFG_PSSR_VAL 0x20 // ???????????
4490 + * PCMCIA and CF Interfaces
4492 +#define CFG_MECR_VAL 0x00000001
4493 +#define CFG_MCMEM0_VAL 0x00010204
4494 +#define CFG_MCMEM1_VAL 0x00010204
4495 +#define CFG_MCATT0_VAL 0x00010204
4496 +#define CFG_MCATT1_VAL 0x00010204
4497 +#define CFG_MCIO0_VAL 0x0000c108
4498 +#define CFG_MCIO1_VAL 0x0001c108
4500 +//#define CONFIG_PXA_PCMCIA 1
4501 +//#define CONFIG_PXA_IDE 1
4503 +#define CONFIG_PCMCIA_SLOT_A 1
4504 +/* just to keep build system happy */
4506 +#define CFG_PCMCIA_MEM_ADDR 0x28000000
4507 +#define CFG_PCMCIA_MEM_SIZE 0x04000000
4509 +#define CFG_IDE_MAXBUS 1
4510 +/* max. 1 IDE bus */
4511 +#define CFG_IDE_MAXDEVICE 1
4512 +/* max. 1 drive per IDE bus */
4514 +#define CFG_ATA_IDE0_OFFSET 0x0000
4516 +#define CFG_ATA_BASE_ADDR 0x20000000
4518 +/* Offset for data I/O */
4519 +#define CFG_ATA_DATA_OFFSET 0x1f0
4521 +/* Offset for normal register accesses */
4522 +#define CFG_ATA_REG_OFFSET 0x1f0
4524 +/* Offset for alternate registers */
4525 +#define CFG_ATA_ALT_OFFSET 0x3f0
4527 +#define CFG_NO_FLASH 1
4528 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
4529 +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
4531 +/*-----------------------------------------------------------------------
4532 + * NAND-FLASH stuff
4533 + *-----------------------------------------------------------------------
4535 +#undef CFG_NAND_LEGACY
4537 +/* NAND debugging */
4538 +//#define CONFIG_MTD_DEBUG
4539 +//#define CONFIG_MTD_DEBUG_VERBOSE 3
4541 +#define CFG_NAND_BASE 0xd4000000
4542 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
4543 +#define NAND_MAX_CHIPS 1
4545 +//#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
4546 +//#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
4548 +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
4549 +#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
4552 + * JFFS2 partitions
4555 +/* No command line, one static partition */
4556 +//#undef CONFIG_JFFS2_CMDLINE
4557 +//#define CONFIG_JFFS2_DEV "nand0"
4558 +//#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
4559 +//#define CONFIG_JFFS2_PART_OFFSET 0x00060000
4561 +/* mtdparts command line support */
4562 +/* Note: fake mtd_id used, no linux mtd map file */
4564 +#define CONFIG_JFFS2_CMDLINE
4565 +#define MTDIDS_DEFAULT "nand0=laze-0"
4566 +//#define MTDPARTS_DEFAULT "mtdparts=laze-0:256k(uboot),128k(env),-(jffs2)"
4567 +#define MTDPARTS_DEFAULT "mtdparts=laze-0:7168k(Logical),-(JFFS2)"
4570 + * SHARP SL NAND logical partition
4572 +#define NAND_LOGICAL 1
4573 +#define NAND_LOGICAL_SIZE 0x700000
4579 +#define CFG_ENV_IS_IN_NAND 1
4580 +#define CFG_ENV_OFFSET 0x40000
4581 +//#define CFG_ENV_OFFSET_REDUND 0x44000
4582 +#define CFG_ENV_SIZE 0x20000
4584 +#endif /* __CONFIG_H */
4585 diff -Nur u-boot-2006-04-18-1106/include/configs/corgi.h u-boot-2006-04-18-1106-new/include/configs/corgi.h
4586 --- u-boot-2006-04-18-1106/include/configs/corgi.h 1970-01-01 00:00:00.000000000 +0000
4587 +++ u-boot-2006-04-18-1106-new/include/configs/corgi.h 2006-07-13 11:19:04.000000000 +0000
4590 + * include/configs/corgi.h
4592 + * Configuration settings for the Sharp Zaurus SL-C7x0/C860.
4594 + * (C) Copyright 2006 Alexander Chukov <sash@pdaXrom.org>
4596 + * portions from adsvix board configuration:
4597 + * (C) Copyright 2004
4598 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
4599 + * (C) Copyright 2002
4600 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4601 + * (C) Copyright 2002
4602 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4603 + * Marius Groeger <mgroeger@sysgo.de>
4605 + * See file CREDITS for list of people who contributed to this
4608 + * This program is free software; you can redistribute it and/or
4609 + * modify it under the terms of the GNU General Public License as
4610 + * published by the Free Software Foundation; either version 2 of
4611 + * the License, or (at your option) any later version.
4613 + * This program is distributed in the hope that it will be useful,
4614 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4615 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4616 + * GNU General Public License for more details.
4618 + * You should have received a copy of the GNU General Public License
4619 + * along with this program; if not, write to the Free Software
4620 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4621 + * MA 02111-1307 USA
4627 +#define CONFIG_SKIP_LOWLEVEL_INIT
4629 +#undef SKIP_CONFIG_RELOCATE_UBOOT
4631 +#undef CONFIG_HARD_I2C
4634 + * High Level Configuration Options
4635 + * (easy to change)
4637 +#define CONFIG_PXA250 1 /* This is an PXA255 CPU */
4638 +#define CONFIG_CORGI 1 /* on Sharp Zaurus Corgi */
4639 +//#define CONFIG_MMC 1
4640 +#define BOARD_LATE_INIT 1
4642 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
4647 + * Size of malloc() pool
4649 +//#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
4650 +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
4651 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
4654 + * select serial console configuration
4656 +#define CONFIG_FFUART 1 /* we use FFUART on Mainstone */
4658 +/* allow to overwrite serial and ethaddr */
4659 +#define CONFIG_BAUDRATE 115200
4660 +//#define CONFIG_DOS_PARTITION 1
4662 +#undef CONFIG_SHOW_BOOT_PROGRESS
4665 +#define CONFIG_BOOTDELAY 1
4666 +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n"
4668 +#define CONFIG_BOOTCOMMAND \
4669 + "if testkey 101 ; " \
4671 + "nand read.logical 0xa0800000 0x00060000 0x00540000; " \
4672 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/ram rw ramdisk_size=8192; " \
4675 + "if testkey 2 ; " \
4677 + "nand read.logical 0xa0800000 0x005a0000 0x00160000; " \
4678 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/mmcblk0p1; " \
4681 + "if testkey 18 ; " \
4683 + "nand read.logical 0xa0800000 0x005a0000 0x00160000; " \
4684 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/hda1; " \
4687 + "if testkey 3 ; " \
4689 + "nand read.logical 0xa0800000 0x005a0000 0x00160000; " \
4690 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/hdc1; " \
4693 + "nand read.logical 0xa0800000 0x005a0000 0x00160000; " \
4694 + "setenv bootargs console=ttyS0,115200 console=tty1 root=/dev/mtdblock2 rootfstype=jffs2; " \
4697 +#define CONFIG_BOOTCOMMAND "" // "run boot_flash"
4700 +#define CONFIG_BOOTARGS "console=ttyS0,115200 console=tty1 root=/dev/ram rw ramdisk_size=8192"
4701 +#define CONFIG_SETUP_MEMORY_TAGS 1
4702 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
4703 +#define CONFIG_INITRD_TAG 1
4705 +#define CONFIG_COMMANDS (( \
4706 + CONFIG_CMD_DFL | \
4717 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
4718 +#include <cmd_confdefs.h>
4721 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
4722 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
4723 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
4727 + * Miscellaneous configurable options
4729 +#define CFG_HUSH_PARSER 1
4730 +#define CFG_PROMPT_HUSH_PS2 "> "
4732 +#define CFG_LONGHELP /* undef to save memory */
4733 +#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
4735 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
4736 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
4737 +#define CFG_MAXARGS 16 /* max number of command args */
4738 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
4739 +#define CFG_DEVICE_NULLDEV 1
4741 +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
4742 +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
4744 +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
4746 +#define CFG_LOAD_ADDR 0xa0800000 /* default load address */
4748 +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
4749 +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
4751 + /* valid baudrates */
4752 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
4754 +#define CFG_MMC_BASE 0xF0000000
4759 + * The stack sizes are set up in start.S using the settings below
4761 +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
4762 +#ifdef CONFIG_USE_IRQ
4763 +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
4764 +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
4768 + * Physical Memory Map
4770 +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
4771 +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
4772 +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
4773 +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
4774 +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
4775 +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
4776 +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
4777 +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
4778 +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
4780 +#define PHYS_FLASH_1 0xd4000000 /* Flash Bank #1 */
4782 +#define CFG_DRAM_BASE 0xa0000000
4783 +#define CFG_DRAM_SIZE 0x04000000
4785 +#define CFG_FLASH_BASE PHYS_FLASH_1
4788 + * GPIO settings for Mainstone
4791 +#define CFG_GPSR0_VAL 0x00708800
4792 +#define CFG_GPSR1_VAL 0x03cf0002
4793 +#define CFG_GPSR2_VAL 0x0021FC00
4794 +#define CFG_GPSR3_VAL 0x00000000
4796 +#define CFG_GPCR0_VAL 0x00001000
4797 +#define CFG_GPCR1_VAL 0x00000000
4798 +#define CFG_GPCR2_VAL 0x00000000
4799 +#define CFG_GPCR3_VAL 0x00000000
4801 +#define CFG_GPDR0_VAL 0xC27B9C04
4802 +#define CFG_GPDR1_VAL 0x00EFAA83
4803 +#define CFG_GPDR2_VAL 0x0E23FC00
4804 +#define CFG_GPDR3_VAL 0x001E1F81
4806 +#define CFG_GAFR0_L_VAL 0x94F00000
4807 +#define CFG_GAFR0_U_VAL 0x015A859A
4808 +#define CFG_GAFR1_L_VAL 0x999A955A
4809 +#define CFG_GAFR1_U_VAL 0x0005A4AA
4810 +#define CFG_GAFR2_L_VAL 0x6AA00000
4811 +#define CFG_GAFR2_U_VAL 0x55A8041A
4812 +#define CFG_GAFR3_L_VAL 0x56AA955A
4813 +#define CFG_GAFR3_U_VAL 0x00000001
4815 +#define CFG_PSSR_VAL 0x20 // ???????????
4818 + * PCMCIA and CF Interfaces
4820 +#define CFG_MECR_VAL 0x00000001
4821 +#define CFG_MCMEM0_VAL 0x00010204
4822 +#define CFG_MCMEM1_VAL 0x00010204
4823 +#define CFG_MCATT0_VAL 0x00010204
4824 +#define CFG_MCATT1_VAL 0x00010204
4825 +#define CFG_MCIO0_VAL 0x0000c108
4826 +#define CFG_MCIO1_VAL 0x0001c108
4828 +//#define CONFIG_PXA_PCMCIA 1
4829 +//#define CONFIG_PXA_IDE 1
4831 +#define CONFIG_PCMCIA_SLOT_A 1
4832 +/* just to keep build system happy */
4834 +#define CFG_PCMCIA_MEM_ADDR 0x28000000
4835 +#define CFG_PCMCIA_MEM_SIZE 0x04000000
4837 +#define CFG_IDE_MAXBUS 1
4838 +/* max. 1 IDE bus */
4839 +#define CFG_IDE_MAXDEVICE 1
4840 +/* max. 1 drive per IDE bus */
4842 +#define CFG_ATA_IDE0_OFFSET 0x0000
4844 +#define CFG_ATA_BASE_ADDR 0x20000000
4846 +/* Offset for data I/O */
4847 +#define CFG_ATA_DATA_OFFSET 0x1f0
4849 +/* Offset for normal register accesses */
4850 +#define CFG_ATA_REG_OFFSET 0x1f0
4852 +/* Offset for alternate registers */
4853 +#define CFG_ATA_ALT_OFFSET 0x3f0
4855 +#define CFG_NO_FLASH 1
4856 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
4857 +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
4859 +/*-----------------------------------------------------------------------
4860 + * NAND-FLASH stuff
4861 + *-----------------------------------------------------------------------
4863 +#undef CFG_NAND_LEGACY
4865 +/* NAND debugging */
4866 +//#define CONFIG_MTD_DEBUG
4867 +//#define CONFIG_MTD_DEBUG_VERBOSE 3
4869 +#define CFG_NAND_BASE 0xd4000000
4870 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
4871 +#define NAND_MAX_CHIPS 1
4873 +//#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
4874 +//#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
4876 +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
4877 +#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
4879 +#define NAND_ALLOW_ERASE_ALL 1
4882 + * JFFS2 partitions
4885 +/* No command line, one static partition */
4886 +//#undef CONFIG_JFFS2_CMDLINE
4887 +//#define CONFIG_JFFS2_DEV "nand0"
4888 +//#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
4889 +//#define CONFIG_JFFS2_PART_OFFSET 0x00060000
4891 +/* mtdparts command line support */
4892 +/* Note: fake mtd_id used, no linux mtd map file */
4894 +#define CONFIG_JFFS2_CMDLINE
4895 +#define MTDIDS_DEFAULT "nand0=laze-0"
4896 +//#define MTDPARTS_DEFAULT "mtdparts=laze-0:256k(uboot),128k(env),-(jffs2)"
4897 +#define MTDPARTS_DEFAULT "mtdparts=laze-0:7168k(Logical),-(JFFS2)"
4900 + * SHARP SL NAND logical partition
4902 +#define NAND_LOGICAL 1
4903 +#define NAND_LOGICAL_SIZE 0x700000
4909 +#define CFG_ENV_IS_IN_NAND 1
4910 +#define CFG_ENV_OFFSET 0x40000
4911 +//#define CFG_ENV_OFFSET_REDUND 0x44000
4912 +#define CFG_ENV_SIZE 0x20000
4914 +#endif /* __CONFIG_H */
4915 --- s/examples/Makefile.orig 2006-12-09 15:08:45.000000000 +0600
4916 +++ s/examples/Makefile 2006-12-09 15:09:00.000000000 +0600
4918 include $(TOPDIR)/config.mk
4920 SREC = hello_world.srec
4921 -BIN = hello_world.bin hello_world
4922 +BIN = hello_world hello_world.bin
4924 ifeq ($(CPU),mpc8xx)
4925 SREC = test_burst.srec
4930 -all: .depend $(OBJS) $(LIB) $(SREC) $(BIN)
4931 +all: .depend $(OBJS) $(LIB) $(BIN) $(SREC)
4933 #########################################################################
4934 $(LIB): .depend $(LIBOBJS)