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35 Message-ID: <1210970183-26615-1-git-send-email-hugo.villeneuve@lyrtech.com>
36 Date: Fri, 16 May 2008 16:36:23 -0400
37 Reply-To: sffsdr Discussion List <SFFSDR@LISTSERV.VT.EDU>
38 Sender: sffsdr Discussion List <SFFSDR@LISTSERV.VT.EDU>
39 From: Hugo Villeneuve <hugo.villeneuve@LYRTECH.COM>
40 Subject: [PATCH] Add support for Lyrtech SFF-SDR board (ARM926EJS)
41 To: SFFSDR@LISTSERV.VT.EDU
45 this is the patch I´m planning on sending to the U-Boot
46 folks so that the SFFSDR is integrated into mainline
49 It is mostly based on the work you have done.
51 I added code to make the EEPROM accessible through
52 the I2C bus. This is needed because we use an I2C
53 switch on the SFFSDR that is turned OFF by default.
54 I also added code to read the MAC address from the
57 I also removed unused stuff specific to the
60 The network and NAND are both working fine with
63 I´m looking forward to your comments.
69 This patch adds support for the Lyrtech SFF-SDR, based
70 on the TI DaVinci architecture (ARM926EJS).
72 Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
77 board/davinci/sffsdr/Makefile | 52 +++++++++
78 board/davinci/sffsdr/board_init.S | 29 +++++
79 board/davinci/sffsdr/config.mk | 24 ++++
80 board/davinci/sffsdr/dv_board.c | 211 +++++++++++++++++++++++++++++++++++++
81 board/davinci/sffsdr/u-boot.lds | 52 +++++++++
82 include/asm-arm/mach-types.h | 13 +++
83 include/configs/davinci_sffsdr.h | 171 ++++++++++++++++++++++++++++++
84 9 files changed, 556 insertions(+), 0 deletions(-)
86 diff --git a/MAKEALL b/MAKEALL
87 index 791eabc..1a0cb37 100755
90 @@ -495,6 +495,7 @@ LIST_ARM9=" \
98 diff --git a/Makefile b/Makefile
99 index 167a717..6280a59 100644
102 @@ -2402,6 +2402,9 @@ davinci_dvevm_config : unconfig
103 davinci_schmoogie_config : unconfig
104 @$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci
106 +davinci_sffsdr_config : unconfig
107 + @$(MKCONFIG) $(@:_config=) arm arm926ejs sffsdr davinci davinci
109 davinci_sonata_config : unconfig
110 @$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci
112 diff --git a/board/davinci/sffsdr/Makefile b/board/davinci/sffsdr/Makefile
114 index 0000000..fa00138
116 +++ b/board/davinci/sffsdr/Makefile
119 +# (C) Copyright 2000, 2001, 2002
120 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
122 +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
124 +# See file CREDITS for list of people who contributed to this
127 +# This program is free software; you can redistribute it and/or
128 +# modify it under the terms of the GNU General Public License as
129 +# published by the Free Software Foundation; either version 2 of
130 +# the License, or (at your option) any later version.
132 +# This program is distributed in the hope that it will be useful,
133 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
134 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
135 +# GNU General Public License for more details.
137 +# You should have received a copy of the GNU General Public License
138 +# along with this program; if not, write to the Free Software
139 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
143 +include $(TOPDIR)/config.mk
145 +LIB = $(obj)lib$(BOARD).a
148 +SOBJS := board_init.o
150 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
151 +OBJS := $(addprefix $(obj),$(COBJS))
152 +SOBJS := $(addprefix $(obj),$(SOBJS))
154 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
155 + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
158 + rm -f $(SOBJS) $(OBJS)
161 + rm -f $(LIB) core *.bak *~ .depend
163 +#########################################################################
164 +# This is for $(obj).depend target
165 +include $(SRCTREE)/rules.mk
167 +sinclude $(obj).depend
169 +#########################################################################
170 diff --git a/board/davinci/sffsdr/board_init.S b/board/davinci/sffsdr/board_init.S
172 index 0000000..22d8adc
174 +++ b/board/davinci/sffsdr/board_init.S
177 + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
179 + * Board-specific low level initialization code. Called at the very end
180 + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
181 + * initialization required.
183 + * This program is free software; you can redistribute it and/or
184 + * modify it under the terms of the GNU General Public License as
185 + * published by the Free Software Foundation; either version 2 of
186 + * the License, or (at your option) any later version.
188 + * This program is distributed in the hope that it will be useful,
189 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
190 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
191 + * GNU General Public License for more details.
193 + * You should have received a copy of the GNU General Public License
194 + * along with this program; if not, write to the Free Software
195 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
196 + * MA 02111-1307 USA
201 +.globl dv_board_init
205 diff --git a/board/davinci/sffsdr/config.mk b/board/davinci/sffsdr/config.mk
207 index 0000000..e8a329c
209 +++ b/board/davinci/sffsdr/config.mk
212 +# (C) Copyright 2002
213 +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
214 +# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
216 +# Lyrtech SFF SDR board (ARM926EJS) cpu
217 +# see http://www.lyrtech.com/ for more information on Lyrtech
219 +# SFF SDR board has 1 bank of 128 MB DDR RAM
221 +# 8000'0000 to 87FF'FFFF
223 +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
224 +# (mem base + reserved)
226 +# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0,
227 +# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc).
229 +# we load ourself to 8400'0000
233 +# Provide at least 32MB spacing between us and the Integrity kernel image
234 +TEXT_BASE = 0x84000000
235 diff --git a/board/davinci/sffsdr/dv_board.c b/board/davinci/sffsdr/dv_board.c
237 index 0000000..a3f60cb
239 +++ b/board/davinci/sffsdr/dv_board.c
242 + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
244 + * Parts are shamelessly stolen from various TI sources, original copyright
246 + * -----------------------------------------------------------------
248 + * Copyright (C) 2004 Texas Instruments.
250 + * ----------------------------------------------------------------------------
251 + * This program is free software; you can redistribute it and/or modify
252 + * it under the terms of the GNU General Public License as published by
253 + * the Free Software Foundation; either version 2 of the License, or
254 + * (at your option) any later version.
256 + * This program is distributed in the hope that it will be useful,
257 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
258 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
259 + * GNU General Public License for more details.
261 + * You should have received a copy of the GNU General Public License
262 + * along with this program; if not, write to the Free Software
263 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
264 + * ----------------------------------------------------------------------------
269 +#include <asm/arch/hardware.h>
270 +#include <asm/arch/emac_defs.h>
272 +DECLARE_GLOBAL_DATA_PTR;
274 +extern void i2c_init(int speed, int slaveaddr);
275 +extern void timer_init(void);
276 +extern int eth_hw_init(void);
280 +/* Works on Always On power domain only (no PD argument) */
281 +void lpsc_on(unsigned int id)
283 + dv_reg_p mdstat, mdctl;
285 + if (id >= DAVINCI_LPSC_GEM)
286 + return; /* Don't work on DSP Power Domain */
288 + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
289 + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
291 + while (REG(PSC_PTSTAT) & 0x01) {;}
293 + if ((*mdstat & 0x1f) == 0x03)
294 + return; /* Already on and enabled */
298 + /* Special treatment for some modules as for sprue14 p.7.4.2 */
299 + if ( (id == DAVINCI_LPSC_VPSSSLV) ||
300 + (id == DAVINCI_LPSC_EMAC) ||
301 + (id == DAVINCI_LPSC_EMAC_WRAPPER) ||
302 + (id == DAVINCI_LPSC_MDIO) ||
303 + (id == DAVINCI_LPSC_USB) ||
304 + (id == DAVINCI_LPSC_ATA) ||
305 + (id == DAVINCI_LPSC_VLYNQ) ||
306 + (id == DAVINCI_LPSC_UHPI) ||
307 + (id == DAVINCI_LPSC_DDR_EMIF) ||
308 + (id == DAVINCI_LPSC_AEMIF) ||
309 + (id == DAVINCI_LPSC_MMC_SD) ||
310 + (id == DAVINCI_LPSC_MEMSTICK) ||
311 + (id == DAVINCI_LPSC_McBSP) ||
312 + (id == DAVINCI_LPSC_GPIO)
316 + REG(PSC_PTCMD) = 0x01;
318 + while (REG(PSC_PTSTAT) & 0x03) {;}
319 + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */
326 + if (REG(PSC_PDSTAT1) & 0x1f)
327 + return; /* Already on */
329 + REG(PSC_GBLCTL) |= 0x01;
330 + REG(PSC_PDCTL1) |= 0x01;
331 + REG(PSC_PDCTL1) &= ~0x100;
332 + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
333 + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
334 + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
335 + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
336 + REG(PSC_PTCMD) = 0x02;
338 + for (i = 0; i < 100; i++) {
339 + if (REG(PSC_EPCPR) & 0x02)
343 + REG(PSC_CHP_SHRTSW) = 0x01;
344 + REG(PSC_PDCTL1) |= 0x100;
345 + REG(PSC_EPCCR) = 0x02;
347 + for (i = 0; i < 100; i++) {
348 + if (!(REG(PSC_PTSTAT) & 0x02))
352 + REG(PSC_GBLCTL) &= ~0x1f;
356 +int board_init(void)
358 + /* arch number of the board */
359 + gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
361 + /* address of boot parameters */
362 + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
364 + /* Workaround for TMS320DM6446 errata 1.3.22 */
365 + REG(PSC_SILVER_BULLET) = 0;
367 + /* Power on required peripherals */
368 + lpsc_on(DAVINCI_LPSC_EMAC);
369 + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
370 + lpsc_on(DAVINCI_LPSC_MDIO);
371 + lpsc_on(DAVINCI_LPSC_I2C);
372 + lpsc_on(DAVINCI_LPSC_UART0);
373 + lpsc_on(DAVINCI_LPSC_TIMER1);
374 + lpsc_on(DAVINCI_LPSC_GPIO);
376 + /* Powerup the DSP */
379 + /* Bringup UART0 out of reset */
380 + REG(UART0_PWREMU_MGMT) = 0x0000e003;
382 + /* Enable GIO3.3V cells used for EMAC */
383 + REG(VDD3P3V_PWDN) = 0;
385 + /* Enable UART0 MUX lines */
388 + /* Enable EMAC and AEMIF pins */
389 + REG(PINMUX0) = 0x80000c1f;
391 + /* Enable I2C pin Mux */
392 + REG(PINMUX1) |= (1 << 7);
394 + /* Set the Bus Priority Register to appropriate value */
402 +int misc_init_r (void)
404 + u_int8_t tmp[20], buf[10];
408 + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
410 + printf ("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
411 + printf ("DDR Clock: %dMHz\n", (clk / 2));
413 + /* Configure I2C switch (PCA9543) to enable channel 0. */
414 + tmp[0] = CFG_I2C_PCA9543_ENABLE_CH0;
415 + if (i2c_write(CFG_I2C_PCA9543_ADDR, 0, CFG_I2C_PCA9543_ADDR_LEN, tmp, 1)) {
416 + printf ("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR);
419 + /* Set Ethernet MAC address from EEPROM.
420 + * We must read 8 bytes because data is stored in little-endian. */
421 + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x05A8, CFG_I2C_EEPROM_ADDR_LEN, buf, 8)) {
422 + printf ("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR);
425 + for (i = 0; i < 6; i++)
428 + if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
429 + sprintf ((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x",
430 + buf[3], buf[2], buf[1], buf[0],
432 + setenv ("ethaddr", (char *)&tmp[0]);
436 + if (!eth_hw_init()) {
437 + printf ("Ethernet init failed\n");
439 + printf ("ETH PHY: %s\n", phy.name);
447 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
448 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
452 diff --git a/board/davinci/sffsdr/u-boot.lds b/board/davinci/sffsdr/u-boot.lds
454 index 0000000..a4fcd1a
456 +++ b/board/davinci/sffsdr/u-boot.lds
459 + * (C) Copyright 2002
460 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
462 + * See file CREDITS for list of people who contributed to this
465 + * This program is free software; you can redistribute it and/or
466 + * modify it under the terms of the GNU General Public License as
467 + * published by the Free Software Foundation; either version 2 of
468 + * the License, or (at your option) any later version.
470 + * This program is distributed in the hope that it will be useful,
471 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
472 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
473 + * GNU General Public License for more details.
475 + * You should have received a copy of the GNU General Public License
476 + * along with this program; if not, write to the Free Software
477 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
478 + * MA 02111-1307 USA
481 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
490 + cpu/arm926ejs/start.o (.text)
494 + .rodata : { *(.rodata) }
496 + .data : { *(.data) }
501 + __u_boot_cmd_start = .;
502 + .u_boot_cmd : { *(.u_boot_cmd) }
503 + __u_boot_cmd_end = .;
507 + .bss (NOLOAD) : { *(.bss) }
510 diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
511 index aaf2ea2..b347857 100644
512 --- a/include/asm-arm/mach-types.h
513 +++ b/include/asm-arm/mach-types.h
514 @@ -1595,6 +1595,7 @@ extern unsigned int __machine_arch_type;
515 #define MACH_TYPE_P300 1602
516 #define MACH_TYPE_XDACOMET 1603
517 #define MACH_TYPE_DEXFLEX2 1604
518 +#define MACH_TYPE_SFFSDR 1657
520 #ifdef CONFIG_ARCH_EBSA110
521 # ifdef machine_arch_type
522 @@ -16500,6 +16501,18 @@ extern unsigned int __machine_arch_type;
523 # define machine_is_schmoogie() (0)
526 +#ifdef CONFIG_MACH_SFFSDR
527 +# ifdef machine_arch_type
528 +# undef machine_arch_type
529 +# define machine_arch_type __machine_arch_type
531 +# define machine_arch_type MACH_TYPE_SFFSDR
533 +# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR)
535 +# define machine_is_sffsdr() (0)
538 #ifdef CONFIG_MACH_AZTOOL
539 # ifdef machine_arch_type
540 # undef machine_arch_type
541 diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
543 index 0000000..a9b480b
545 +++ b/include/configs/davinci_sffsdr.h
548 + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
550 + * This program is free software; you can redistribute it and/or
551 + * modify it under the terms of the GNU General Public License as
552 + * published by the Free Software Foundation; either version 2 of
553 + * the License, or (at your option) any later version.
555 + * This program is distributed in the hope that it will be useful,
556 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
557 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
558 + * GNU General Public License for more details.
560 + * You should have received a copy of the GNU General Public License
561 + * along with this program; if not, write to the Free Software
562 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
563 + * MA 02111-1307 USA
568 +#include <asm/sizes.h>
574 +#define CFG_NAND_LARGEPAGE
575 +#define CFG_USE_NAND
576 +/*===================*/
577 +/* SoC Configuration */
578 +/*===================*/
579 +#define CONFIG_ARM926EJS /* arm926ejs CPU core */
580 +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
581 +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
582 +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
584 +/*==================================================*/
585 +/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
586 +/*==================================================*/
587 +#define CFG_I2C_EEPROM_ADDR_LEN 2
588 +#define CFG_I2C_EEPROM_ADDR 0x50
589 +#define CFG_EEPROM_PAGE_WRITE_BITS 5
590 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
594 +#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
595 +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
596 +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
597 +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
598 +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
599 +#define CONFIG_STACKSIZE (256*1024) /* regular stack */
600 +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
601 +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
602 +#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
603 +/*====================*/
604 +/* Serial Driver info */
605 +/*====================*/
607 +#define CFG_NS16550_SERIAL
608 +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
609 +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
610 +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
611 +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
612 +#define CONFIG_BAUDRATE 115200 /* Default baud rate */
613 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
614 +/*===================*/
615 +/* I2C Configuration */
616 +/*===================*/
617 +#define CONFIG_HARD_I2C
618 +#define CONFIG_DRIVER_DAVINCI_I2C
619 +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
620 +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
621 +/*==================================*/
622 +/* Network & Ethernet Configuration */
623 +/*==================================*/
624 +#define CONFIG_DRIVER_TI_EMAC
626 +#define CONFIG_BOOTP_DEFAULT
627 +#define CONFIG_BOOTP_DNS
628 +#define CONFIG_BOOTP_DNS2
629 +#define CONFIG_BOOTP_SEND_HOSTNAME
630 +#define CONFIG_NET_RETRY_COUNT 10
631 +#define CONFIG_OVERWRITE_ETHADDR_ONCE
632 +/*=====================*/
633 +/* Flash & Environment */
634 +/*=====================*/
635 +#undef CFG_ENV_IS_IN_FLASH
636 +#define CFG_NO_FLASH
637 +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
638 +#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */
639 +#define CFG_ENV_SIZE SZ_128K
640 +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
641 +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
642 +#define CFG_NAND_BASE 0x02000000
643 +#define CFG_NAND_HW_ECC
644 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
645 +#define NAND_MAX_CHIPS 1
646 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
647 +/*=====================*/
648 +/* Board related stuff */
649 +/*=====================*/
650 +/*==========================================*/
651 +/* I2C switch definitions for PCA9543 chip */
652 +/* on Lyrtech SFF SDR board. */
653 +/*==========================================*/
654 +#define CFG_I2C_PCA9543_ADDR 0x70
655 +#define CFG_I2C_PCA9543_ADDR_LEN 0 /* This chip has a single register. */
656 +#define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
657 +/*==============================*/
658 +/* U-Boot general configuration */
659 +/*==============================*/
660 +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
661 +#define CONFIG_MISC_INIT_R
662 +#undef CONFIG_BOOTDELAY
663 +#define CONFIG_BOOTFILE "uImage" /* Boot file name */
664 +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
665 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
666 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
667 +#define CFG_MAXARGS 16 /* max number of command args */
668 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
669 +#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
670 +#define CONFIG_VERSION_VARIABLE
671 +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
672 +#define CFG_HUSH_PARSER
673 +#define CFG_PROMPT_HUSH_PS2 "> "
674 +#define CONFIG_CMDLINE_EDITING
675 +#define CFG_LONGHELP
676 +#define CONFIG_CRC32_VERIFY
677 +#define CONFIG_MX_CYCLIC
679 + * Define this to load an Integrity kernel.
681 +#define CONFIG_CMD_ELF
684 +/*===================*/
685 +/* Linux Information */
686 +/*===================*/
687 +#define LINUX_BOOT_PARAM_ADDR 0x80000100
688 +#define CONFIG_CMDLINE_TAG
689 +#define CONFIG_SETUP_MEMORY_TAGS
690 +#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
691 +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
692 +/*=================*/
693 +/* U-Boot commands */
694 +/*=================*/
695 +#include <config_cmd_default.h>
696 +#define CONFIG_CMD_ASKENV
697 +#define CONFIG_CMD_DHCP
698 +#define CONFIG_CMD_DIAG
699 +#define CONFIG_CMD_I2C
700 +#define CONFIG_CMD_MII
701 +#define CONFIG_CMD_PING
702 +#define CONFIG_CMD_SAVES
703 +#define CONFIG_CMD_NAND
704 +#define CONFIG_CMD_EEPROM
705 +#undef CONFIG_CMD_BDI
706 +#undef CONFIG_CMD_FPGA
707 +#undef CONFIG_CMD_SETGETDCR
708 +#undef CONFIG_CMD_FLASH
709 +#undef CONFIG_CMD_IMLS
710 +/*=======================*/
711 +/* KGDB support (if any) */
712 +/*=======================*/
713 +#ifdef CONFIG_CMD_KGDB
714 +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
715 +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
717 +#endif /* __CONFIG_H */