2 events/arm/armv6/events | 43 +++++++++++++++++++++----------------------
3 1 file changed, 21 insertions(+), 22 deletions(-)
5 Index: oprofile-0.9.3/events/arm/armv6/events
6 ===================================================================
7 --- oprofile-0.9.3.orig/events/arm/armv6/events 2007-07-16 19:22:17.000000000 +0100
8 +++ oprofile-0.9.3/events/arm/armv6/events 2007-09-28 11:13:32.000000000 +0100
12 -event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
13 -event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
14 -event:0x02 counters:1,2 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency
15 -event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of Instruction MicroTLB misses
16 -event:0x04 counters:1,2 um:zero minimum:500 name:DTLB_MISS : number of Data MicroTLB misses
17 -event:0x05 counters:1,2 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
18 -event:0x06 counters:1,2 um:zero minimum:500 name:BR_INST_MISS_PRED : branch mispredicted
19 -event:0x07 counters:1,2 um:zero minimum:500 name:INSN_EXECUTED : instructions executed
20 -event:0x09 counters:1,2 um:zero minimum:500 name:DCACHE_ACCESS : data cache access, cacheable locations
21 -event:0x0a counters:1,2 um:zero minimum:500 name:DCACHE_ACCESS_ALL : data cache access, all locations
22 -event:0x0b counters:1,2 um:zero minimum:500 name:DCACHE_MISS : data cache miss
23 -event:0x0c counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
24 -event:0x0d counters:1,2 um:zero minimum:500 name:PC_CHANGE : number of times the program counter was changed without a mode switch
25 -event:0x0f counters:1,2 um:zero minimum:500 name:TLB_MISS : Main TLB miss
26 -event:0x10 counters:1,2 um:zero minimum:500 name:EXP_EXTERNAL : Explict external data access
27 -event:0x11 counters:1,2 um:zero minimum:500 name:LSU_STALL : cycles stalled because Load Store request queque is full
28 -event:0x12 counters:1,2 um:zero minimum:500 name:WRITE_DRAIN : Times write buffer was drained
29 -event:0x20 counters:1,2 um:zero minimum:500 name:ETMEXTOUT0 : nuber of cycles ETMEXTOUT[0] signal was asserted
30 -event:0x21 counters:1,2 um:zero minimum:500 name:ETMEXTOUT1 : nuber of cycles ETMEXTOUT[1] signal was asserted
31 -event:0x22 counters:1,2 um:zero minimum:500 name:ETMEXTOUT_BOTH : nuber of cycles both ETMEXTOUT [0] and [1] were asserted * 2
32 -event:0xff counters:1,2 um:zero minimum:500 name:CPU_CYCLES2 : clock cycles counter
33 -event:0xfe counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
34 +event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
35 +event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
36 +event:0x02 counters:0,1 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency
37 +event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of Instruction MicroTLB misses
38 +event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of Data MicroTLB misses
39 +event:0x05 counters:0,1 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
40 +event:0x06 counters:0,1 um:zero minimum:500 name:BR_INST_MISS_PRED : branch mispredicted
41 +event:0x07 counters:0,1 um:zero minimum:500 name:INSN_EXECUTED : instructions executed
42 +event:0x09 counters:0,1 um:zero minimum:500 name:DCACHE_ACCESS : data cache access, cacheable locations
43 +event:0x0a counters:0,1 um:zero minimum:500 name:DCACHE_ACCESS_ALL : data cache access, all locations
44 +event:0x0b counters:0,1 um:zero minimum:500 name:DCACHE_MISS : data cache miss
45 +event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
46 +event:0x0d counters:0,1 um:zero minimum:500 name:PC_CHANGE : number of times the program counter was changed without a mode switch
47 +event:0x0f counters:0,1 um:zero minimum:500 name:TLB_MISS : Main TLB miss
48 +event:0x10 counters:0,1 um:zero minimum:500 name:EXP_EXTERNAL : Explict external data access
49 +event:0x11 counters:0,1 um:zero minimum:500 name:LSU_STALL : cycles stalled because Load Store request queque is full
50 +event:0x12 counters:0,1 um:zero minimum:500 name:WRITE_DRAIN : Times write buffer was drained
51 +event:0x20 counters:0,1 um:zero minimum:500 name:ETMEXTOUT0 : nuber of cycles ETMEXTOUT[0] signal was asserted
52 +event:0x21 counters:0,1 um:zero minimum:500 name:ETMEXTOUT1 : nuber of cycles ETMEXTOUT[1] signal was asserted
53 +event:0x22 counters:0,1 um:zero minimum:500 name:ETMEXTOUT_BOTH : nuber of cycles both ETMEXTOUT [0] and [1] were asserted * 2
54 +event:0xff counters:0,1,2 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
projects / vuplus_openembedded / blob