code.vuplus.com Git - vuplus_openembedded/blob - packages/linux/linux-rp-2.6.24/tosa/0025-Signed-off-by-Dmitry-Baryshkov-dbaryshkov-gmail.co.patch

   1 From 39717c1328f6aa13330eded0e0e268993cfd1eea Mon Sep 17 00:00:00 2001
   2 From: Dmitry Baryshkov <dbaryshkov@gmail.com>
   3 Date: Tue, 12 Feb 2008 10:39:53 +0300
   4 Subject: [PATCH 25/64] Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
   5
   6 ---
   7  arch/arm/mach-pxa/Makefile  |    2 +-
   8  arch/arm/mach-pxa/devices.c |  401 +++++++++++++++++++++++++++++++++++++++++++
   9  2 files changed, 402 insertions(+), 1 deletions(-)
  10  create mode 100644 arch/arm/mach-pxa/devices.c
  11
  12 diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
  13 index 5cb0216..f276d24 100644
  14 --- a/arch/arm/mach-pxa/Makefile
  15 +++ b/arch/arm/mach-pxa/Makefile
  16 @@ -4,7 +4,7 @@
  17
  18  # Common support (must be linked before board specific support)
  19  obj-y                          += clock.o generic.o irq.o dma.o \
  20 -                                  time.o gpio.o
  21 +                                  time.o gpio.o devices.o
  22  obj-$(CONFIG_PXA25x)           += pxa25x.o
  23  obj-$(CONFIG_PXA27x)           += pxa27x.o
  24  obj-$(CONFIG_PXA3xx)           += pxa3xx.o mfp.o
  25 diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
  26 new file mode 100644
  27 index 0000000..928131a
  28 --- /dev/null
  29 +++ b/arch/arm/mach-pxa/devices.c
  30 @@ -0,0 +1,401 @@
  31 +#include <linux/module.h>
  32 +#include <linux/kernel.h>
  33 +#include <linux/init.h>
  34 +#include <linux/platform_device.h>
  35 +#include <linux/dma-mapping.h>
  36 +
  37 +#include <asm/arch/gpio.h>
  38 +#include <asm/arch/udc.h>
  39 +#include <asm/arch/pxafb.h>
  40 +#include <asm/arch/mmc.h>
  41 +#include <asm/arch/irda.h>
  42 +#include <asm/arch/i2c.h>
  43 +#include <asm/arch/ohci.h>
  44 +
  45 +#include "devices.h"
  46 +
  47 +#ifdef CONFIG_PXA25x
  48 +
  49 +static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  50 +
  51 +static struct resource pxa25x_resource_ssp[] = {
  52 +       [0] = {
  53 +               .start  = 0x41000000,
  54 +               .end    = 0x4100001f,
  55 +               .flags  = IORESOURCE_MEM,
  56 +       },
  57 +       [1] = {
  58 +               .start  = IRQ_SSP,
  59 +               .end    = IRQ_SSP,
  60 +               .flags  = IORESOURCE_IRQ,
  61 +       },
  62 +       [2] = {
  63 +               /* DRCMR for RX */
  64 +               .start  = 13,
  65 +               .end    = 13,
  66 +               .flags  = IORESOURCE_DMA,
  67 +       },
  68 +       [3] = {
  69 +               /* DRCMR for TX */
  70 +               .start  = 14,
  71 +               .end    = 14,
  72 +               .flags  = IORESOURCE_DMA,
  73 +       },
  74 +};
  75 +
  76 +struct platform_device pxa25x_device_ssp = {
  77 +       .name           = "pxa25x-ssp",
  78 +       .id             = 0,
  79 +       .dev            = {
  80 +               .dma_mask = &pxa25x_ssp_dma_mask,
  81 +               .coherent_dma_mask = DMA_BIT_MASK(32),
  82 +       },
  83 +       .resource       = pxa25x_resource_ssp,
  84 +       .num_resources  = ARRAY_SIZE(pxa25x_resource_ssp),
  85 +};
  86 +
  87 +static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  88 +
  89 +static struct resource pxa25x_resource_nssp[] = {
  90 +       [0] = {
  91 +               .start  = 0x41400000,
  92 +               .end    = 0x4140002f,
  93 +               .flags  = IORESOURCE_MEM,
  94 +       },
  95 +       [1] = {
  96 +               .start  = IRQ_NSSP,
  97 +               .end    = IRQ_NSSP,
  98 +               .flags  = IORESOURCE_IRQ,
  99 +       },
 100 +       [2] = {
 101 +               /* DRCMR for RX */
 102 +               .start  = 15,
 103 +               .end    = 15,
 104 +               .flags  = IORESOURCE_DMA,
 105 +       },
 106 +       [3] = {
 107 +               /* DRCMR for TX */
 108 +               .start  = 16,
 109 +               .end    = 16,
 110 +               .flags  = IORESOURCE_DMA,
 111 +       },
 112 +};
 113 +
 114 +struct platform_device pxa25x_device_nssp = {
 115 +       .name           = "pxa25x-nssp",
 116 +       .id             = 1,
 117 +       .dev            = {
 118 +               .dma_mask = &pxa25x_nssp_dma_mask,
 119 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 120 +       },
 121 +       .resource       = pxa25x_resource_nssp,
 122 +       .num_resources  = ARRAY_SIZE(pxa25x_resource_nssp),
 123 +};
 124 +
 125 +static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
 126 +
 127 +static struct resource pxa25x_resource_assp[] = {
 128 +       [0] = {
 129 +               .start  = 0x41500000,
 130 +               .end    = 0x4150002f,
 131 +               .flags  = IORESOURCE_MEM,
 132 +       },
 133 +       [1] = {
 134 +               .start  = IRQ_ASSP,
 135 +               .end    = IRQ_ASSP,
 136 +               .flags  = IORESOURCE_IRQ,
 137 +       },
 138 +       [2] = {
 139 +               /* DRCMR for RX */
 140 +               .start  = 23,
 141 +               .end    = 23,
 142 +               .flags  = IORESOURCE_DMA,
 143 +       },
 144 +       [3] = {
 145 +               /* DRCMR for TX */
 146 +               .start  = 24,
 147 +               .end    = 24,
 148 +               .flags  = IORESOURCE_DMA,
 149 +       },
 150 +};
 151 +
 152 +struct platform_device pxa25x_device_assp = {
 153 +       /* ASSP is basically equivalent to NSSP */
 154 +       .name           = "pxa25x-nssp",
 155 +       .id             = 2,
 156 +       .dev            = {
 157 +               .dma_mask = &pxa25x_assp_dma_mask,
 158 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 159 +       },
 160 +       .resource       = pxa25x_resource_assp,
 161 +       .num_resources  = ARRAY_SIZE(pxa25x_resource_assp),
 162 +};
 163 +#endif /* CONFIG_PXA25x */
 164 +
 165 +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 166 +
 167 +static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
 168 +
 169 +static struct resource pxa27x_resource_ohci[] = {
 170 +       [0] = {
 171 +               .start  = 0x4C000000,
 172 +               .end    = 0x4C00ff6f,
 173 +               .flags  = IORESOURCE_MEM,
 174 +       },
 175 +       [1] = {
 176 +               .start  = IRQ_USBH1,
 177 +               .end    = IRQ_USBH1,
 178 +               .flags  = IORESOURCE_IRQ,
 179 +       },
 180 +};
 181 +
 182 +struct platform_device pxa27x_device_ohci = {
 183 +       .name           = "pxa27x-ohci",
 184 +       .id             = -1,
 185 +       .dev            = {
 186 +               .dma_mask = &pxa27x_ohci_dma_mask,
 187 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 188 +       },
 189 +       .num_resources  = ARRAY_SIZE(pxa27x_resource_ohci),
 190 +       .resource       = pxa27x_resource_ohci,
 191 +};
 192 +
 193 +void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
 194 +{
 195 +       pxa_register_device(&pxa27x_device_ohci, info);
 196 +}
 197 +
 198 +static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
 199 +
 200 +static struct resource pxa27x_resource_ssp1[] = {
 201 +       [0] = {
 202 +               .start  = 0x41000000,
 203 +               .end    = 0x4100003f,
 204 +               .flags  = IORESOURCE_MEM,
 205 +       },
 206 +       [1] = {
 207 +               .start  = IRQ_SSP,
 208 +               .end    = IRQ_SSP,
 209 +               .flags  = IORESOURCE_IRQ,
 210 +       },
 211 +       [2] = {
 212 +               /* DRCMR for RX */
 213 +               .start  = 13,
 214 +               .end    = 13,
 215 +               .flags  = IORESOURCE_DMA,
 216 +       },
 217 +       [3] = {
 218 +               /* DRCMR for TX */
 219 +               .start  = 14,
 220 +               .end    = 14,
 221 +               .flags  = IORESOURCE_DMA,
 222 +       },
 223 +};
 224 +
 225 +struct platform_device pxa27x_device_ssp1 = {
 226 +       .name           = "pxa27x-ssp",
 227 +       .id             = 0,
 228 +       .dev            = {
 229 +               .dma_mask = &pxa27x_ssp1_dma_mask,
 230 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 231 +       },
 232 +       .resource       = pxa27x_resource_ssp1,
 233 +       .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp1),
 234 +};
 235 +
 236 +static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
 237 +
 238 +static struct resource pxa27x_resource_ssp2[] = {
 239 +       [0] = {
 240 +               .start  = 0x41700000,
 241 +               .end    = 0x4170003f,
 242 +               .flags  = IORESOURCE_MEM,
 243 +       },
 244 +       [1] = {
 245 +               .start  = IRQ_SSP2,
 246 +               .end    = IRQ_SSP2,
 247 +               .flags  = IORESOURCE_IRQ,
 248 +       },
 249 +       [2] = {
 250 +               /* DRCMR for RX */
 251 +               .start  = 15,
 252 +               .end    = 15,
 253 +               .flags  = IORESOURCE_DMA,
 254 +       },
 255 +       [3] = {
 256 +               /* DRCMR for TX */
 257 +               .start  = 16,
 258 +               .end    = 16,
 259 +               .flags  = IORESOURCE_DMA,
 260 +       },
 261 +};
 262 +
 263 +struct platform_device pxa27x_device_ssp2 = {
 264 +       .name           = "pxa27x-ssp",
 265 +       .id             = 1,
 266 +       .dev            = {
 267 +               .dma_mask = &pxa27x_ssp2_dma_mask,
 268 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 269 +       },
 270 +       .resource       = pxa27x_resource_ssp2,
 271 +       .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp2),
 272 +};
 273 +
 274 +static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
 275 +
 276 +static struct resource pxa27x_resource_ssp3[] = {
 277 +       [0] = {
 278 +               .start  = 0x41900000,
 279 +               .end    = 0x4190003f,
 280 +               .flags  = IORESOURCE_MEM,
 281 +       },
 282 +       [1] = {
 283 +               .start  = IRQ_SSP3,
 284 +               .end    = IRQ_SSP3,
 285 +               .flags  = IORESOURCE_IRQ,
 286 +       },
 287 +       [2] = {
 288 +               /* DRCMR for RX */
 289 +               .start  = 66,
 290 +               .end    = 66,
 291 +               .flags  = IORESOURCE_DMA,
 292 +       },
 293 +       [3] = {
 294 +               /* DRCMR for TX */
 295 +               .start  = 67,
 296 +               .end    = 67,
 297 +               .flags  = IORESOURCE_DMA,
 298 +       },
 299 +};
 300 +
 301 +struct platform_device pxa27x_device_ssp3 = {
 302 +       .name           = "pxa27x-ssp",
 303 +       .id             = 2,
 304 +       .dev            = {
 305 +               .dma_mask = &pxa27x_ssp3_dma_mask,
 306 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 307 +       },
 308 +       .resource       = pxa27x_resource_ssp3,
 309 +       .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp3),
 310 +};
 311 +#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
 312 +
 313 +#ifdef CONFIG_PXA3xx
 314 +static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
 315 +
 316 +static struct resource pxa3xx_resource_ssp4[] = {
 317 +       [0] = {
 318 +               .start  = 0x41a00000,
 319 +               .end    = 0x41a0003f,
 320 +               .flags  = IORESOURCE_MEM,
 321 +       },
 322 +       [1] = {
 323 +               .start  = IRQ_SSP4,
 324 +               .end    = IRQ_SSP4,
 325 +               .flags  = IORESOURCE_IRQ,
 326 +       },
 327 +       [2] = {
 328 +               /* DRCMR for RX */
 329 +               .start  = 2,
 330 +               .end    = 2,
 331 +               .flags  = IORESOURCE_DMA,
 332 +       },
 333 +       [3] = {
 334 +               /* DRCMR for TX */
 335 +               .start  = 3,
 336 +               .end    = 3,
 337 +               .flags  = IORESOURCE_DMA,
 338 +       },
 339 +};
 340 +
 341 +struct platform_device pxa3xx_device_ssp4 = {
 342 +       /* PXA3xx SSP is basically equivalent to PXA27x */
 343 +       .name           = "pxa27x-ssp",
 344 +       .id             = 3,
 345 +       .dev            = {
 346 +               .dma_mask = &pxa3xx_ssp4_dma_mask,
 347 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 348 +       },
 349 +       .resource       = pxa3xx_resource_ssp4,
 350 +       .num_resources  = ARRAY_SIZE(pxa3xx_resource_ssp4),
 351 +};
 352 +
 353 +static struct resource pxa3xx_resources_mci2[] = {
 354 +       [0] = {
 355 +               .start  = 0x42000000,
 356 +               .end    = 0x42000fff,
 357 +               .flags  = IORESOURCE_MEM,
 358 +       },
 359 +       [1] = {
 360 +               .start  = IRQ_MMC2,
 361 +               .end    = IRQ_MMC2,
 362 +               .flags  = IORESOURCE_IRQ,
 363 +       },
 364 +       [2] = {
 365 +               .start  = 93,
 366 +               .end    = 93,
 367 +               .flags  = IORESOURCE_DMA,
 368 +       },
 369 +       [3] = {
 370 +               .start  = 94,
 371 +               .end    = 94,
 372 +               .flags  = IORESOURCE_DMA,
 373 +       },
 374 +};
 375 +
 376 +struct platform_device pxa3xx_device_mci2 = {
 377 +       .name           = "pxa2xx-mci",
 378 +       .id             = 1,
 379 +       .dev            = {
 380 +               .dma_mask = &pxamci_dmamask,
 381 +               .coherent_dma_mask =    0xffffffff,
 382 +       },
 383 +       .num_resources  = ARRAY_SIZE(pxa3xx_resources_mci2),
 384 +       .resource       = pxa3xx_resources_mci2,
 385 +};
 386 +
 387 +void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
 388 +{
 389 +       pxa_register_device(&pxa3xx_device_mci2, info);
 390 +}
 391 +
 392 +static struct resource pxa3xx_resources_mci3[] = {
 393 +       [0] = {
 394 +               .start  = 0x42500000,
 395 +               .end    = 0x42500fff,
 396 +               .flags  = IORESOURCE_MEM,
 397 +       },
 398 +       [1] = {
 399 +               .start  = IRQ_MMC3,
 400 +               .end    = IRQ_MMC3,
 401 +               .flags  = IORESOURCE_IRQ,
 402 +       },
 403 +       [2] = {
 404 +               .start  = 100,
 405 +               .end    = 100,
 406 +               .flags  = IORESOURCE_DMA,
 407 +       },
 408 +       [3] = {
 409 +               .start  = 101,
 410 +               .end    = 101,
 411 +               .flags  = IORESOURCE_DMA,
 412 +       },
 413 +};
 414 +
 415 +struct platform_device pxa3xx_device_mci3 = {
 416 +       .name           = "pxa2xx-mci",
 417 +       .id             = 2,
 418 +       .dev            = {
 419 +               .dma_mask = &pxamci_dmamask,
 420 +               .coherent_dma_mask = 0xffffffff,
 421 +       },
 422 +       .num_resources  = ARRAY_SIZE(pxa3xx_resources_mci3),
 423 +       .resource       = pxa3xx_resources_mci3,
 424 +};
 425 +
 426 +void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
 427 +{
 428 +       pxa_register_device(&pxa3xx_device_mci3, info);
 429 +}
 430 +
 431 +#endif /* CONFIG_PXA3xx */
 432 --
 433 1.5.3.8
 434