code.vuplus.com Git - vuplus_openembedded/blob - packages/linux/linux-omap/mru-make-dpll4-m4-ck-programmable.diff

   1 From 38e48da3c27d38b05bed4572930240e73e4dfb22 Mon Sep 17 00:00:00 2001
   2 From: Mans Rullgard <mans@mansr.com>
   3 Date: Tue, 22 Jul 2008 01:31:11 +0100
   4 Subject: [PATCH] ARM: OMAP: make dpll4_m4_ck programmable with clk_set_rate()
   5
   6 Filling the set_rate and round_rate fields of dpll4_m4_ck makes
   7 this clock programmable through clk_set_rate().  This is needed
   8 to give omapfb control over the dss1_alwon_fck rate.
   9 ---
  10  arch/arm/mach-omap2/clock34xx.h |    2 ++
  11  1 files changed, 2 insertions(+), 0 deletions(-)
  12
  13 diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
  14 index 08789c8..1032577 100644
  15 --- a/arch/arm/mach-omap2/clock34xx.h
  16 +++ b/arch/arm/mach-omap2/clock34xx.h
  17 @@ -821,6 +821,8 @@ static struct clk dpll4_m4_ck = {
  18                                 PARENT_CONTROLS_CLOCK,
  19         .clkdm          = { .name = "dpll4_clkdm" },
  20         .recalc         = &omap2_clksel_recalc,
  21 +       .set_rate       = &omap2_clksel_set_rate,
  22 +       .round_rate     = &omap2_clksel_round_rate,
  23  };
  24
  25  /* The PWRDN bit is apparently only available on 3430ES2 and above */
  26 --
  27 1.5.6.3
  28