code.vuplus.com Git - vuplus_openvuplus_3.0/blob - meta-bsp/common/recipes/linux/linux-vuplus-3.1.1/rt5372_kernel_3.1.1.patch

   1 diff -Naur linux.orig/drivers/net/wireless/rt2x00/rt2800.h linux/drivers/net/wireless/rt2x00/rt2800.h\r
   2 --- linux.orig/drivers/net/wireless/rt2x00/rt2800.h     2011-11-11 21:19:27.000000000 +0100\r
   3 +++ linux/drivers/net/wireless/rt2x00/rt2800.h  2014-02-23 20:21:13.000000000 +0100\r
   4 @@ -68,6 +68,7 @@\r
   5  #define RF3322                         0x000c\r
   6  #define RF3853                         0x000d\r
   7  #define RF5370                         0x5370\r
   8 +#define RF5372                         0x5372\r
   9  #define RF5390                         0x5390\r
  10  \r
  11  /*\r
  12 diff -Naur linux.orig/drivers/net/wireless/rt2x00/rt2800lib.c linux/drivers/net/wireless/rt2x00/rt2800lib.c\r
  13 --- linux.orig/drivers/net/wireless/rt2x00/rt2800lib.c  2011-11-11 21:19:27.000000000 +0100\r
  14 +++ linux/drivers/net/wireless/rt2x00/rt2800lib.c       2014-02-23 20:25:27.000000000 +0100\r
  15 @@ -402,7 +402,8 @@\r
  16  \r
  17         if (rt2x00_is_pci(rt2x00dev)) {\r
  18                 if (rt2x00_rt(rt2x00dev, RT3572) ||\r
  19 -                   rt2x00_rt(rt2x00dev, RT5390)) {\r
  20 +                   rt2x00_rt(rt2x00dev, RT5390) ||\r
  21 +                   rt2x00_rt(rt2x00dev, RT5392)) {\r
  22                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);\r
  23                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);\r
  24                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);\r
  25 @@ -1128,8 +1129,10 @@\r
  26                            !(filter_flags & FIF_CONTROL));\r
  27         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,\r
  28                            !(filter_flags & FIF_PSPOLL));\r
  29 -       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);\r
  30 -       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);\r
  31 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,\r
  32 +                          !(filter_flags & FIF_CONTROL));\r
  33 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,\r
  34 +                          !(filter_flags & FIF_CONTROL));\r
  35         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,\r
  36                            !(filter_flags & FIF_CONTROL));\r
  37         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);\r
  38 @@ -1867,19 +1870,25 @@\r
  39                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);\r
  40         }\r
  41  \r
  42 -       if (rt2x00_rf(rt2x00dev, RF2020) ||\r
  43 -           rt2x00_rf(rt2x00dev, RF3020) ||\r
  44 -           rt2x00_rf(rt2x00dev, RF3021) ||\r
  45 -           rt2x00_rf(rt2x00dev, RF3022) ||\r
  46 -           rt2x00_rf(rt2x00dev, RF3320))\r
  47 +       switch (rt2x00dev->chip.rf) {\r
  48 +       case RF2020:\r
  49 +       case RF3020:\r
  50 +       case RF3021:\r
  51 +       case RF3022:\r
  52 +       case RF3320:\r
  53                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);\r
  54 -       else if (rt2x00_rf(rt2x00dev, RF3052))\r
  55 +               break;\r
  56 +       case RF3052:\r
  57                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);\r
  58 -       else if (rt2x00_rf(rt2x00dev, RF5370) ||\r
  59 -                rt2x00_rf(rt2x00dev, RF5390))\r
  60 +               break;\r
  61 +       case RF5370:\r
  62 +       case RF5372:\r
  63 +       case RF5390:\r
  64                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);\r
  65 -       else\r
  66 +               break;\r
  67 +       default:\r
  68                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);\r
  69 +       }\r
  70  \r
  71         /*\r
  72          * Change BBP settings\r
  73 @@ -1890,7 +1899,8 @@\r
  74         rt2800_bbp_write(rt2x00dev, 86, 0);\r
  75  \r
  76         if (rf->channel <= 14) {\r
  77 -               if (!rt2x00_rt(rt2x00dev, RT5390)) {\r
  78 +               if (!rt2x00_rt(rt2x00dev, RT5390) &&\r
  79 +                       !rt2x00_rt(rt2x00dev, RT5392)) {\r
  80                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,\r
  81                                      &rt2x00dev->cap_flags)) {\r
  82                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);\r
  83 @@ -2420,7 +2430,8 @@\r
  84                     rt2x00_rt(rt2x00dev, RT3071) ||\r
  85                     rt2x00_rt(rt2x00dev, RT3090) ||\r
  86                     rt2x00_rt(rt2x00dev, RT3390) ||\r
  87 -                   rt2x00_rt(rt2x00dev, RT5390))\r
  88 +                   rt2x00_rt(rt2x00dev, RT5390) ||\r
  89 +                   rt2x00_rt(rt2x00dev, RT5392))\r
  90                         return 0x1c + (2 * rt2x00dev->lna_gain);\r
  91                 else\r
  92                         return 0x2e + rt2x00dev->lna_gain;\r
  93 @@ -2555,7 +2566,8 @@\r
  94         } else if (rt2x00_rt(rt2x00dev, RT3572)) {\r
  95                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);\r
  96                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);\r
  97 -       } else if (rt2x00_rt(rt2x00dev, RT5390)) {\r
  98 +       } else if (rt2x00_rt(rt2x00dev, RT5390) ||\r
  99 +                          rt2x00_rt(rt2x00dev, RT5392)) {\r
 100                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);\r
 101                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);\r
 102                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);\r
 103 @@ -2934,7 +2946,8 @@\r
 104                      rt2800_wait_bbp_ready(rt2x00dev)))\r
 105                 return -EACCES;\r
 106  \r
 107 -       if (rt2x00_rt(rt2x00dev, RT5390)) {\r
 108 +       if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 109 +               rt2x00_rt(rt2x00dev, RT5392)) {\r
 110                 rt2800_bbp_read(rt2x00dev, 4, &value);\r
 111                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);\r
 112                 rt2800_bbp_write(rt2x00dev, 4, value);\r
 113 @@ -2942,19 +2955,22 @@\r
 114  \r
 115         if (rt2800_is_305x_soc(rt2x00dev) ||\r
 116             rt2x00_rt(rt2x00dev, RT3572) ||\r
 117 -           rt2x00_rt(rt2x00dev, RT5390))\r
 118 +           rt2x00_rt(rt2x00dev, RT5390) ||\r
 119 +           rt2x00_rt(rt2x00dev, RT5392))\r
 120                 rt2800_bbp_write(rt2x00dev, 31, 0x08);\r
 121  \r
 122         rt2800_bbp_write(rt2x00dev, 65, 0x2c);\r
 123         rt2800_bbp_write(rt2x00dev, 66, 0x38);\r
 124  \r
 125 -       if (rt2x00_rt(rt2x00dev, RT5390))\r
 126 +       if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 127 +               rt2x00_rt(rt2x00dev, RT5392))\r
 128                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);\r
 129  \r
 130         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {\r
 131                 rt2800_bbp_write(rt2x00dev, 69, 0x16);\r
 132                 rt2800_bbp_write(rt2x00dev, 73, 0x12);\r
 133 -       } else if (rt2x00_rt(rt2x00dev, RT5390)) {\r
 134 +       } else if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 135 +                          rt2x00_rt(rt2x00dev, RT5392)) {\r
 136                 rt2800_bbp_write(rt2x00dev, 69, 0x12);\r
 137                 rt2800_bbp_write(rt2x00dev, 73, 0x13);\r
 138                 rt2800_bbp_write(rt2x00dev, 75, 0x46);\r
 139 @@ -2972,7 +2988,8 @@\r
 140             rt2x00_rt(rt2x00dev, RT3090) ||\r
 141             rt2x00_rt(rt2x00dev, RT3390) ||\r
 142             rt2x00_rt(rt2x00dev, RT3572) ||\r
 143 -           rt2x00_rt(rt2x00dev, RT5390)) {\r
 144 +           rt2x00_rt(rt2x00dev, RT5390) ||\r
 145 +           rt2x00_rt(rt2x00dev, RT5392)) {\r
 146                 rt2800_bbp_write(rt2x00dev, 79, 0x13);\r
 147                 rt2800_bbp_write(rt2x00dev, 80, 0x05);\r
 148                 rt2800_bbp_write(rt2x00dev, 81, 0x33);\r
 149 @@ -2984,64 +3001,88 @@\r
 150         }\r
 151  \r
 152         rt2800_bbp_write(rt2x00dev, 82, 0x62);\r
 153 -       if (rt2x00_rt(rt2x00dev, RT5390))\r
 154 +       if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 155 +               rt2x00_rt(rt2x00dev, RT5392))\r
 156                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);\r
 157         else\r
 158                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);\r
 159  \r
 160         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))\r
 161                 rt2800_bbp_write(rt2x00dev, 84, 0x19);\r
 162 -       else if (rt2x00_rt(rt2x00dev, RT5390))\r
 163 +       else if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 164 +                        rt2x00_rt(rt2x00dev, RT5392))\r
 165                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);\r
 166         else\r
 167                 rt2800_bbp_write(rt2x00dev, 84, 0x99);\r
 168  \r
 169 -       if (rt2x00_rt(rt2x00dev, RT5390))\r
 170 +       if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 171 +               rt2x00_rt(rt2x00dev, RT5392))\r
 172                 rt2800_bbp_write(rt2x00dev, 86, 0x38);\r
 173         else\r
 174                 rt2800_bbp_write(rt2x00dev, 86, 0x00);\r
 175  \r
 176 +       if (rt2x00_rt(rt2x00dev, RT5392))\r
 177 +               rt2800_bbp_write(rt2x00dev, 88, 0x90);\r
 178 +\r
 179         rt2800_bbp_write(rt2x00dev, 91, 0x04);\r
 180  \r
 181 -       if (rt2x00_rt(rt2x00dev, RT5390))\r
 182 +       if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 183 +               rt2x00_rt(rt2x00dev, RT5392))\r
 184                 rt2800_bbp_write(rt2x00dev, 92, 0x02);\r
 185         else\r
 186                 rt2800_bbp_write(rt2x00dev, 92, 0x00);\r
 187  \r
 188 +       if (rt2x00_rt(rt2x00dev, RT5392)) {\r
 189 +               rt2800_bbp_write(rt2x00dev, 95, 0x9a);\r
 190 +               rt2800_bbp_write(rt2x00dev, 98, 0x12);\r
 191 +       }\r
 192 +\r
 193         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||\r
 194             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||\r
 195             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||\r
 196             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||\r
 197             rt2x00_rt(rt2x00dev, RT3572) ||\r
 198             rt2x00_rt(rt2x00dev, RT5390) ||\r
 199 +           rt2x00_rt(rt2x00dev, RT5392) ||\r
 200             rt2800_is_305x_soc(rt2x00dev))\r
 201                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);\r
 202         else\r
 203                 rt2800_bbp_write(rt2x00dev, 103, 0x00);\r
 204  \r
 205 -       if (rt2x00_rt(rt2x00dev, RT5390))\r
 206 +       if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 207 +               rt2x00_rt(rt2x00dev, RT5392))\r
 208                 rt2800_bbp_write(rt2x00dev, 104, 0x92);\r
 209  \r
 210         if (rt2800_is_305x_soc(rt2x00dev))\r
 211                 rt2800_bbp_write(rt2x00dev, 105, 0x01);\r
 212 -       else if (rt2x00_rt(rt2x00dev, RT5390))\r
 213 +       else if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 214 +                        rt2x00_rt(rt2x00dev, RT5392))\r
 215                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);\r
 216         else\r
 217                 rt2800_bbp_write(rt2x00dev, 105, 0x05);\r
 218  \r
 219         if (rt2x00_rt(rt2x00dev, RT5390))\r
 220                 rt2800_bbp_write(rt2x00dev, 106, 0x03);\r
 221 +       else if (rt2x00_rt(rt2x00dev, RT5392))\r
 222 +               rt2800_bbp_write(rt2x00dev, 106, 0x12);\r
 223         else\r
 224                 rt2800_bbp_write(rt2x00dev, 106, 0x35);\r
 225  \r
 226 -       if (rt2x00_rt(rt2x00dev, RT5390))\r
 227 +       if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 228 +               rt2x00_rt(rt2x00dev, RT5392))\r
 229                 rt2800_bbp_write(rt2x00dev, 128, 0x12);\r
 230  \r
 231 +       if (rt2x00_rt(rt2x00dev, RT5392)) {\r
 232 +               rt2800_bbp_write(rt2x00dev, 134, 0xd0);\r
 233 +               rt2800_bbp_write(rt2x00dev, 135, 0xf6);\r
 234 +       }\r
 235 +\r
 236         if (rt2x00_rt(rt2x00dev, RT3071) ||\r
 237             rt2x00_rt(rt2x00dev, RT3090) ||\r
 238             rt2x00_rt(rt2x00dev, RT3390) ||\r
 239             rt2x00_rt(rt2x00dev, RT3572) ||\r
 240 -           rt2x00_rt(rt2x00dev, RT5390)) {\r
 241 +           rt2x00_rt(rt2x00dev, RT5390) ||\r
 242 +           rt2x00_rt(rt2x00dev, RT5392)) {\r
 243                 rt2800_bbp_read(rt2x00dev, 138, &value);\r
 244  \r
 245                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);\r
 246 @@ -3053,7 +3094,8 @@\r
 247                 rt2800_bbp_write(rt2x00dev, 138, value);\r
 248         }\r
 249  \r
 250 -       if (rt2x00_rt(rt2x00dev, RT5390)) {\r
 251 +       if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 252 +               rt2x00_rt(rt2x00dev, RT5392)) {\r
 253                 int ant, div_mode;\r
 254  \r
 255                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);\r
 256 @@ -3179,13 +3221,15 @@\r
 257             !rt2x00_rt(rt2x00dev, RT3390) &&\r
 258             !rt2x00_rt(rt2x00dev, RT3572) &&\r
 259             !rt2x00_rt(rt2x00dev, RT5390) &&\r
 260 +           !rt2x00_rt(rt2x00dev, RT5392) &&\r
 261             !rt2800_is_305x_soc(rt2x00dev))\r
 262                 return 0;\r
 263  \r
 264         /*\r
 265          * Init RF calibration.\r
 266          */\r
 267 -       if (rt2x00_rt(rt2x00dev, RT5390)) {\r
 268 +       if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 269 +               rt2x00_rt(rt2x00dev, RT5392)) {\r
 270                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);\r
 271                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);\r
 272                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);\r
 273 @@ -3403,6 +3447,66 @@\r
 274                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);\r
 275                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);\r
 276                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);\r
 277 +       }       else if (rt2x00_rt(rt2x00dev, RT5392)) {\r
 278 +                       rt2800_rfcsr_write(rt2x00dev, 1, 0x17);\r
 279 +                       rt2800_rfcsr_write(rt2x00dev, 2, 0x80);\r
 280 +                       rt2800_rfcsr_write(rt2x00dev, 3, 0x88);\r
 281 +                       rt2800_rfcsr_write(rt2x00dev, 5, 0x10);\r
 282 +                       rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);\r
 283 +                       rt2800_rfcsr_write(rt2x00dev, 7, 0x00);\r
 284 +                       rt2800_rfcsr_write(rt2x00dev, 10, 0x53);\r
 285 +                       rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);\r
 286 +                       rt2800_rfcsr_write(rt2x00dev, 12, 0x46);\r
 287 +                       rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);\r
 288 +                       rt2800_rfcsr_write(rt2x00dev, 14, 0x00);\r
 289 +                       rt2800_rfcsr_write(rt2x00dev, 15, 0x00);\r
 290 +                       rt2800_rfcsr_write(rt2x00dev, 16, 0x00);\r
 291 +                       rt2800_rfcsr_write(rt2x00dev, 18, 0x03);\r
 292 +                       rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);\r
 293 +                       rt2800_rfcsr_write(rt2x00dev, 20, 0x00);\r
 294 +                       rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);\r
 295 +                       rt2800_rfcsr_write(rt2x00dev, 22, 0x20);\r
 296 +                       rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);\r
 297 +                       rt2800_rfcsr_write(rt2x00dev, 24, 0x44);\r
 298 +                       rt2800_rfcsr_write(rt2x00dev, 25, 0x80);\r
 299 +                       rt2800_rfcsr_write(rt2x00dev, 26, 0x82);\r
 300 +                       rt2800_rfcsr_write(rt2x00dev, 27, 0x09);\r
 301 +                       rt2800_rfcsr_write(rt2x00dev, 28, 0x00);\r
 302 +                       rt2800_rfcsr_write(rt2x00dev, 29, 0x10);\r
 303 +                       rt2800_rfcsr_write(rt2x00dev, 30, 0x10);\r
 304 +                       rt2800_rfcsr_write(rt2x00dev, 31, 0x80);\r
 305 +                       rt2800_rfcsr_write(rt2x00dev, 32, 0x20);\r
 306 +                       rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);\r
 307 +                       rt2800_rfcsr_write(rt2x00dev, 34, 0x07);\r
 308 +                       rt2800_rfcsr_write(rt2x00dev, 35, 0x12);\r
 309 +                       rt2800_rfcsr_write(rt2x00dev, 36, 0x00);\r
 310 +                       rt2800_rfcsr_write(rt2x00dev, 37, 0x08);\r
 311 +                       rt2800_rfcsr_write(rt2x00dev, 38, 0x89);\r
 312 +                       rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);\r
 313 +                       rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);\r
 314 +                       rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);\r
 315 +                       rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);\r
 316 +                       rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);\r
 317 +                       rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);\r
 318 +                       rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);\r
 319 +                       rt2800_rfcsr_write(rt2x00dev, 46, 0x73);\r
 320 +                       rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);\r
 321 +                       rt2800_rfcsr_write(rt2x00dev, 48, 0x10);\r
 322 +                       rt2800_rfcsr_write(rt2x00dev, 49, 0x94);\r
 323 +                       rt2800_rfcsr_write(rt2x00dev, 50, 0x94);\r
 324 +                       rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);\r
 325 +                       rt2800_rfcsr_write(rt2x00dev, 52, 0x48);\r
 326 +                       rt2800_rfcsr_write(rt2x00dev, 53, 0x44);\r
 327 +                       rt2800_rfcsr_write(rt2x00dev, 54, 0x38);\r
 328 +                       rt2800_rfcsr_write(rt2x00dev, 55, 0x43);\r
 329 +                       rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);\r
 330 +                       rt2800_rfcsr_write(rt2x00dev, 57, 0x00);\r
 331 +                       rt2800_rfcsr_write(rt2x00dev, 58, 0x39);\r
 332 +                       rt2800_rfcsr_write(rt2x00dev, 59, 0x07);\r
 333 +                       rt2800_rfcsr_write(rt2x00dev, 60, 0x45);\r
 334 +                       rt2800_rfcsr_write(rt2x00dev, 61, 0x91);\r
 335 +                       rt2800_rfcsr_write(rt2x00dev, 62, 0x39);\r
 336 +                       rt2800_rfcsr_write(rt2x00dev, 63, 0x07);\r
 337         }\r
 338  \r
 339         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {\r
 340 @@ -3470,7 +3574,8 @@\r
 341                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);\r
 342         }\r
 343  \r
 344 -       if (!rt2x00_rt(rt2x00dev, RT5390)) {\r
 345 +       if (!rt2x00_rt(rt2x00dev, RT5390) &&\r
 346 +               !rt2x00_rt(rt2x00dev, RT5392)) {\r
 347                 /*\r
 348                  * Set back to initial state\r
 349                  */\r
 350 @@ -3498,7 +3603,8 @@\r
 351         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);\r
 352         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);\r
 353  \r
 354 -       if (!rt2x00_rt(rt2x00dev, RT5390)) {\r
 355 +       if (!rt2x00_rt(rt2x00dev, RT5390) &&\r
 356 +               !rt2x00_rt(rt2x00dev, RT5392)) {\r
 357                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);\r
 358                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);\r
 359                 if (rt2x00_rt(rt2x00dev, RT3070) ||\r
 360 @@ -3566,7 +3672,8 @@\r
 361                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);\r
 362         }\r
 363  \r
 364 -       if (rt2x00_rt(rt2x00dev, RT5390)) {\r
 365 +       if (rt2x00_rt(rt2x00dev, RT5390) ||\r
 366 +               rt2x00_rt(rt2x00dev, RT5392)) {\r
 367                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);\r
 368                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);\r
 369                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);\r
 370 @@ -3850,7 +3957,8 @@\r
 371          * RT53xx: defined in "EEPROM_CHIP_ID" field\r
 372          */\r
 373         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);\r
 374 -       if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)\r
 375 +       if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||\r
 376 +               rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)\r
 377                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);\r
 378         else\r
 379                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);\r
 380 @@ -3858,15 +3966,19 @@\r
 381         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),\r
 382                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));\r
 383  \r
 384 -       if (!rt2x00_rt(rt2x00dev, RT2860) &&\r
 385 -           !rt2x00_rt(rt2x00dev, RT2872) &&\r
 386 -           !rt2x00_rt(rt2x00dev, RT2883) &&\r
 387 -           !rt2x00_rt(rt2x00dev, RT3070) &&\r
 388 -           !rt2x00_rt(rt2x00dev, RT3071) &&\r
 389 -           !rt2x00_rt(rt2x00dev, RT3090) &&\r
 390 -           !rt2x00_rt(rt2x00dev, RT3390) &&\r
 391 -           !rt2x00_rt(rt2x00dev, RT3572) &&\r
 392 -           !rt2x00_rt(rt2x00dev, RT5390)) {\r
 393 +       switch (rt2x00dev->chip.rt) {\r
 394 +       case RT2860:\r
 395 +       case RT2872:\r
 396 +       case RT2883:\r
 397 +       case RT3070:\r
 398 +       case RT3071:\r
 399 +       case RT3090:\r
 400 +       case RT3390:\r
 401 +       case RT3572:\r
 402 +       case RT5390:\r
 403 +       case RT5392:\r
 404 +               break;\r
 405 +       default:\r
 406                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");\r
 407                 return -ENODEV;\r
 408         }\r
 409 @@ -3883,6 +3995,7 @@\r
 410         case RF3052:\r
 411         case RF3320:\r
 412         case RF5370:\r
 413 +       case RF5372:\r
 414         case RF5390:\r
 415                 break;\r
 416         default:\r
 417 @@ -4189,6 +4302,7 @@\r
 418                    rt2x00_rf(rt2x00dev, RF3022) ||\r
 419                    rt2x00_rf(rt2x00dev, RF3320) ||\r
 420                    rt2x00_rf(rt2x00dev, RF5370) ||\r
 421 +                  rt2x00_rf(rt2x00dev, RF5372) ||\r
 422                    rt2x00_rf(rt2x00dev, RF5390)) {\r
 423                 spec->num_channels = 14;\r
 424                 spec->channels = rf_vals_3x;\r
 425 diff -Naur linux.orig/drivers/net/wireless/rt2x00/rt2x00.h linux/drivers/net/wireless/rt2x00/rt2x00.h\r
 426 --- linux.orig/drivers/net/wireless/rt2x00/rt2x00.h     2011-11-11 21:19:27.000000000 +0100\r
 427 +++ linux/drivers/net/wireless/rt2x00/rt2x00.h  2014-02-23 20:20:33.000000000 +0100\r
 428 @@ -191,7 +191,8 @@\r
 429  #define RT3572         0x3572\r
 430  #define RT3593         0x3593  /* PCIe */\r
 431  #define RT3883         0x3883  /* WSOC */\r
 432 -#define RT5390         0x5390  /* 2.4GHz */\r
 433 +#define RT5390         0x5390  /* 2.4GHz */\r
 434 +#define RT5392          0x5392 /* 2.4GHz */\r
 435  \r
 436         u16 rf;\r
 437         u16 rev;\r