,"fp" : ["http://archive.vuplus.com/download/fp", "fp.files", "/dev/bcm_mu;"]
,"vfd" : ["http://archive.vuplus.com/download/vfd", "vfd.files", "/dev/bcm_vfd_ctrl;"]
}
+ elif info == "solose":
+ fwlist= [
+ ("fpga", _("FPGA"))
+ ,("fp", _("Front Processor"))
+ ]
+ fwdata= {
+ "fpga" : ["http://archive.vuplus.com/download/fpga", "fpga.files", "/dev/fpga_dp;/dev/misc/dp;"]
+ ,"fp" : ["http://archive.vuplus.com/download/fp", "fp.files", "/dev/bcm_mu;"]
+ }
import os, fcntl, thread
STATUS_READY = 0