diff --git a/Makefile b/Makefile
-index cc988e1..16701c5 100644
+index 8bfc891..e9bf61a 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ ifeq ($(ARCH),ppc)
# The "tools" are needed early, so put this first
# Don't include stuff already done in $(LIBS)
-@@ -2562,6 +2562,12 @@ SMN42_config : unconfig
+@@ -2565,6 +2565,12 @@ SMN42_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292
#########################################################################
+#########################################################################
diff --git a/board/omap3530beagle/clock.c b/board/omap3530beagle/clock.c
new file mode 100644
-index 0000000..964525b
+index 0000000..1f4b4f3
--- /dev/null
+++ b/board/omap3530beagle/clock.c
-@@ -0,0 +1,316 @@
+@@ -0,0 +1,314 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ */
+
+#include <common.h>
-+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/clocks_omap3.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
-+#include <asm/arch/sys_info.h>
+#include <environment.h>
+#include <command.h>
+
+
diff --git a/board/omap3530beagle/lowlevel_init.S b/board/omap3530beagle/lowlevel_init.S
new file mode 100644
-index 0000000..7ec4d05
+index 0000000..1f9a0e9
--- /dev/null
+++ b/board/omap3530beagle/lowlevel_init.S
-@@ -0,0 +1,361 @@
+@@ -0,0 +1,360 @@
+/*
+ * Board specific setup info
+ *
+
+#include <config.h>
+#include <version.h>
-+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks_omap3.h>
+
+
diff --git a/board/omap3530beagle/mem.c b/board/omap3530beagle/mem.c
new file mode 100644
-index 0000000..bee96c3
+index 0000000..fb803be
--- /dev/null
+++ b/board/omap3530beagle/mem.c
-@@ -0,0 +1,251 @@
+@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ */
+
+#include <common.h>
-+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h>
+}
diff --git a/board/omap3530beagle/nand.c b/board/omap3530beagle/nand.c
new file mode 100644
-index 0000000..4a8b6e4
+index 0000000..2f94684
--- /dev/null
+++ b/board/omap3530beagle/nand.c
-@@ -0,0 +1,409 @@
+@@ -0,0 +1,408 @@
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+
+#include <common.h>
+#include <asm/io.h>
-+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <linux/mtd/nand_ecc.h>
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
diff --git a/board/omap3530beagle/omap3530beagle.c b/board/omap3530beagle/omap3530beagle.c
new file mode 100644
-index 0000000..1daf42c
+index 0000000..7d9a566
--- /dev/null
+++ b/board/omap3530beagle/omap3530beagle.c
-@@ -0,0 +1,781 @@
+@@ -0,0 +1,388 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ * MA 02111-1307 USA
+ */
+#include <common.h>
-+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
-+#include <asm/arch/sys_info.h>
+#include <asm/arch/mem.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+#endif
+
-+/*
-+ * Dummy functions to handle errors for EABI incompatibility
-+ */
-+void raise(void)
-+{
-+}
-+
-+void abort(void)
-+{
-+}
++#define NOT_EARLY 0
+
++/* Permission values for registers -Full fledged permissions to all */
++#define UNLOCK_1 0xFFFFFFFF
++#define UNLOCK_2 0x00000000
++#define UNLOCK_3 0x0000FFFF
+
-+/*******************************************************
++/******************************************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
-+ ******************************************************/
++ *****************************************************************************/
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
-+/*****************************************
++/******************************************************************************
+ * Routine: board_init
+ * Description: Early hardware init.
-+ *****************************************/
++ *****************************************************************************/
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
-+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE; /* board id for Linux */
-+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */
++ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
++ /* board id for Linux */
++ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
++ /* boot param addr */
++ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
-+/*****************************************
++/******************************************************************************
+ * Routine: secure_unlock
-+ * Description: Setup security registers for access
-+ * (GP Device only)
-+ *****************************************/
++ * Description: Setup security registers for access
++ * (GP Device only)
++ *****************************************************************************/
+void secure_unlock_mem(void)
+{
-+ /* Permission values for registers -Full fledged permissions to all */
-+#define UNLOCK_1 0xFFFFFFFF
-+#define UNLOCK_2 0x00000000
-+#define UNLOCK_3 0x0000FFFF
+ /* Protection Module Register Target APE (PM_RT) */
+ __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
+ __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
+}
+
-+/**********************************************************
++/******************************************************************************
+ * Routine: secureworld_exit()
+ * Description: If chip is EMU and boot type is external
+ * configure secure registers and exit secure world
-+ * general use.
-+ ***********************************************************/
++ * general use.
++ *****************************************************************************/
+void secureworld_exit()
+{
+ unsigned long i;
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
+}
+
-+/**********************************************************
++/******************************************************************************
+ * Routine: setup_auxcr()
+ * Description: Write to AuxCR desired value using SMI.
-+ * general use.
-+ ***********************************************************/
++ * general use.
++ *****************************************************************************/
+void setup_auxcr()
+{
+ unsigned long i;
+ __asm__ __volatile__("mov r12, %0":"=r"(j));
+}
+
-+/**********************************************************
++/******************************************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP/EMU(special) type, unlock the SRAM for
-+ * general use.
-+ ***********************************************************/
++ * general use.
++ *****************************************************************************/
+void try_unlock_memory()
+{
+ int mode;
+ /* if GP device unlock device SRAM for general use */
+ /* secure code breaks for Secure/Emulation device - HS/E/T */
+ mode = get_device_type();
-+ if (mode == GP_DEVICE) {
++ if (mode == GP_DEVICE)
+ secure_unlock_mem();
-+ }
-+ /* If device is EMU and boot is XIP external booting
-+ * Unlock firewalls and disable L2 and put chip
++
++ /* If device is EMU and boot is XIP external booting
++ * Unlock firewalls and disable L2 and put chip
+ * out of secure world
+ */
+ /* Assuming memories are unlocked by the demon who put us in SDRAM */
+ return;
+}
+
-+/**********************************************************
++/******************************************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
-+ * - Called path is with SRAM stack.
-+ **********************************************************/
++ * - Called path is with SRAM stack.
++ *****************************************************************************/
+void s_init(void)
+{
+ int in_sdram = running_in_sdram();
+
-+#ifdef CONFIG_3430VIRTIO
-+ in_sdram = 0; /* allow setup from memory for Virtio */
-+#endif
+ watchdog_init();
+
+ try_unlock_memory();
+
-+ /* Right now flushing at low MPU speed. Need to move after clock init */
++ /* Right now flushing at low MPU speed.
++ Need to move after clock init */
+ v7_flush_dcache_all(get_device_type());
+#ifndef CONFIG_ICACHE_OFF
+ icache_enable();
+ if (!in_sdram)
+ sdrc_init();
+}
-+/*******************************************************
++
++/******************************************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
-+ ********************************************************/
++ *****************************************************************************/
+int misc_init_r(void)
+{
++
+ unsigned char byte;
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ return (0);
+}
+
-+/******************************************************
++
++/******************************************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
-+ ******************************************************/
++ *****************************************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+ } while (pending);
+}
+
-+/****************************************
++/******************************************************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
-+ *****************************************/
++ *****************************************************************************/
+void watchdog_init(void)
+{
-+ /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
++ /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
+ * either taken care of by ROM (HS/EMU) or not accessible (GP).
-+ * We need to take care of WD2-MPU or take a PRCM reset. WD3
++ * We need to take care of WD2-MPU or take a PRCM reset. WD3
+ * should not be running and does not generate a PRCM reset.
+ */
+
+ __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
+}
+
-+/*******************************************************************
-+ * Routine:ether_init
-+ * Description: take the Ethernet controller out of reset and wait
-+ * for the EEPROM load to complete.
-+ ******************************************************************/
-+void ether_init(void)
-+{
-+#ifdef CONFIG_DRIVER_LAN91C96
-+ int cnt = 20;
-+
-+ __raw_writew(0x0, LAN_RESET_REGISTER);
-+ do {
-+ __raw_writew(0x1, LAN_RESET_REGISTER);
-+ udelay(100);
-+ if (cnt == 0)
-+ goto h4reset_err_out;
-+ --cnt;
-+ } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
-+
-+ cnt = 20;
-+
-+ do {
-+ __raw_writew(0x0, LAN_RESET_REGISTER);
-+ udelay(100);
-+ if (cnt == 0)
-+ goto h4reset_err_out;
-+ --cnt;
-+ } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
-+ udelay(1000);
-+
-+ *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
-+ udelay(1000);
-+
-+ h4reset_err_out:
-+ return;
-+#endif
-+}
-+
-+/**********************************************
++/******************************************************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
-+ **********************************************/
++ *****************************************************************************/
+int dram_init(void)
+{
-+#define NOT_EARLY 0
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned int size0 = 0, size1 = 0;
+ u32 mtype, btype;
+
+ btype = get_board_type();
+ mtype = get_mem_type();
-+#ifndef CONFIG_3430ZEBU
-+ /* fixme... dont know why this func is crashing in ZeBu */
++
+ display_board_info(btype);
-+#endif
-+ /* If a second bank of DDR is attached to CS1 this is
++
++ /* If a second bank of DDR is attached to CS1 this is
+ * where it can be started. Early init code will init
+ * memory on CS0.
+ */
-+ if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
++ if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED))
+ do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
-+ }
++
+ size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+ size1 = get_sdr_cs_size(SDRC_CS1_OSET);
+
+ return 0;
+}
+
-+#define MUX_VAL(OFFSET,VALUE)\
-+ __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
++/******************************************************************************
++ * Routine: set_muxconf_regs
++ * Description: Setting up the configuration Mux registers specific to the
++ * hardware. Many pins need to be moved from protect to primary
++ * mode.
++ *****************************************************************************/
++void set_muxconf_regs(void)
++{
++ MUX_DEFAULT_ES2();
++}
+
-+#define CP(x) (CONTROL_PADCONF_##x)
++#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
++/******************************************************************************
++ * Routine: nand+_init
++ * Description: Set up nand for nand and jffs2 commands
++ *****************************************************************************/
++void nand_init(void)
++{
++ extern flash_info_t flash_info[];
++
++ nand_probe(CFG_NAND_ADDR);
++ if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN)
++ print_size(nand_dev_desc[0].totlen, "\n");
++
++#ifdef CFG_JFFS2_MEM_NAND
++ flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
++ /* only read kernel single meg partition */
++ flash_info[CFG_JFFS2_FIRST_BANK].size = 1024 * 1024 * 2;
++ /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
++ flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024;
++ /* ?, ram for now, open question, copy to RAM or adapt for NAND */
++ flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000;
++#endif
++}
++#endif
++
++/******************************************************************************
++ * Dummy function to handle errors for EABI incompatibility
++ *****************************************************************************/
++void raise(void)
++{
++}
++
++/******************************************************************************
++ * Dummy function to handle errors for EABI incompatibility
++ *****************************************************************************/
++void abort(void)
++{
++}
+diff --git a/board/omap3530beagle/sys_info.c b/board/omap3530beagle/sys_info.c
+new file mode 100644
+index 0000000..a275557
+--- /dev/null
++++ b/board/omap3530beagle/sys_info.c
+@@ -0,0 +1,309 @@
+/*
-+ * IEN - Input Enable
-+ * IDIS - Input Disable
-+ * PTD - Pull type Down
-+ * PTU - Pull type Up
-+ * DIS - Pull type selection is inactive
-+ * EN - Pull type selection is active
-+ * M0 - Mode 0
-+ * The commented string gives the final mux configuration for that pin
-+ */
-+#define MUX_DEFAULT_ES2()\
-+ /*SDRC*/\
-+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
-+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
-+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
-+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
-+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
-+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
-+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
-+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
-+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
-+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
-+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
-+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
-+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
-+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
-+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
-+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
-+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
-+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
-+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
-+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
-+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
-+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
-+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
-+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
-+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
-+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
-+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
-+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
-+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
-+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
-+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
-+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
-+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
-+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
-+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
-+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
-+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
-+ /*GPMC*/\
-+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
-+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
-+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
-+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
-+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
-+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
-+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
-+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
-+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
-+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
-+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
-+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
-+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
-+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
-+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
-+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
-+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
-+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
-+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
-+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
-+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
-+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
-+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
-+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
-+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
-+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
-+ MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
-+ MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
-+ MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
-+ MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
-+ /* For Beagle Rev 1 boards */\
-+ /*MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0))\
-+ MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0))\
-+ MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0))\
-+ MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0))\
-+ MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4))\
-+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\
-+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4))*/\
-+ /* For Beagle Rev 2 boards*/\
-+ MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0))\
-+ MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0))\
-+ MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1))\
-+ MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1))\
-+ MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0))\
-+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0))\
-+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0))\
-+ /* till here */\
-+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
-+ MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
-+ MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
-+ MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
-+ MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
-+ MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
-+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
-+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
-+ /*DSS*/\
-+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
-+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
-+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
-+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
-+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
-+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
-+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
-+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
-+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
-+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
-+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
-+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
-+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
-+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
-+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
-+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
-+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
-+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
-+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
-+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
-+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
-+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
-+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
-+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
-+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
-+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
-+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
-+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
-+ /*CAMERA*/\
-+ MUX_VAL(CP(CAM_HS ), (IEN | PTU | EN | M0)) /*CAM_HS */\
-+ MUX_VAL(CP(CAM_VS ), (IEN | PTU | EN | M0)) /*CAM_VS */\
-+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
-+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
-+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98 - CAM_RESET*/\
-+ MUX_VAL(CP(CAM_D0 ), (IEN | PTD | DIS | M0)) /*CAM_D0 */\
-+ MUX_VAL(CP(CAM_D1 ), (IEN | PTD | DIS | M0)) /*CAM_D1 */\
-+ MUX_VAL(CP(CAM_D2 ), (IEN | PTD | DIS | M0)) /*CAM_D2 */\
-+ MUX_VAL(CP(CAM_D3 ), (IEN | PTD | DIS | M0)) /*CAM_D3 */\
-+ MUX_VAL(CP(CAM_D4 ), (IEN | PTD | DIS | M0)) /*CAM_D4 */\
-+ MUX_VAL(CP(CAM_D5 ), (IEN | PTD | DIS | M0)) /*CAM_D5 */\
-+ MUX_VAL(CP(CAM_D6 ), (IEN | PTD | DIS | M0)) /*CAM_D6 */\
-+ MUX_VAL(CP(CAM_D7 ), (IEN | PTD | DIS | M0)) /*CAM_D7 */\
-+ MUX_VAL(CP(CAM_D8 ), (IEN | PTD | DIS | M0)) /*CAM_D8 */\
-+ MUX_VAL(CP(CAM_D9 ), (IEN | PTD | DIS | M0)) /*CAM_D9 */\
-+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
-+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
-+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
-+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
-+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
-+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
-+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
-+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
-+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
-+ /*Audio Interface */\
-+ MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
-+ MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
-+ MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
-+ MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
-+ /*Expansion card */\
-+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
-+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
-+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
-+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
-+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
-+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
-+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
-+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
-+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
-+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
-+ /*Wireless LAN */\
-+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
-+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
-+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
-+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
-+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
-+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
-+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
-+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
-+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
-+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
-+ /*Bluetooth*/\
-+ MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
-+ MUX_VAL(CP(McBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
-+ MUX_VAL(CP(McBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
-+ MUX_VAL(CP(McBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
-+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
-+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
-+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
-+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\
-+ /*Modem Interface */\
-+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
-+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\
-+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\
-+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
-+ MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX */\
-+ MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX */\
-+ MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX */\
-+ MUX_VAL(CP(McBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
-+ MUX_VAL(CP(McBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
-+ MUX_VAL(CP(McBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157 - BT_WAKEUP*/\
-+ MUX_VAL(CP(McBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
-+ MUX_VAL(CP(McBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
-+ MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS */\
-+ MUX_VAL(CP(McBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
-+ MUX_VAL(CP(McBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162 */\
-+ /*Serial Interface*/\
-+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
-+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
-+ MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
-+ MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
-+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
-+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
-+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
-+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
-+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0 */\
-+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1 */\
-+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2 */\
-+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3 */\
-+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4 */\
-+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5 */\
-+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6 */\
-+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7 */\
-+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
-+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
-+ MUX_VAL(CP(I2C2_SCL), (IDIS | PTU | DIS | M4)) /*GPIO_168*/\
-+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
-+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
-+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
-+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
-+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
-+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
-+ MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
-+ MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
-+ MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
-+ MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
-+ MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
-+ MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176 - NOR_DPD*/\
-+ MUX_VAL(CP(McSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\
-+ MUX_VAL(CP(McSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
-+ MUX_VAL(CP(McSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
-+ MUX_VAL(CP(McSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
-+ MUX_VAL(CP(McSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
-+ MUX_VAL(CP(McSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
-+ /*Control and debug */\
-+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
-+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
-+ MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
-+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 - PEN_IRQ */\
-+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
-+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP */\
-+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 - LCD_ENVDD*/\
-+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 - LAN_INTR0*/\
-+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 - MMC2_WP*/\
-+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8 - LCD_ENBKL*/\
-+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\
-+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1 */\
-+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
-+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
-+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB1_CLK*/\
-+ MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA0*/\
-+ MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA1*/\
-+ MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA2*/\
-+ MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA7*/\
-+ MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA4*/\
-+ MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA5*/\
-+ MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA6*/\
-+ MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA3*/\
-+ MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DIR*/\
-+ MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_NXT*/\
-+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\
-+ MUX_VAL(CP(ETK_D15), (IEN | PTU | EN | M4)) /*GPIO_29*/\
-+ MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
-+ MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
-+ MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
-+ MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
-+ MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
-+ MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
-+ MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
-+ MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
-+ MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
-+ MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
-+ MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
-+ MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
-+ MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
-+ MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
-+ MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
-+ MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
-+ MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
-+ MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
-+ MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
-+ MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
-+ MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
-+ MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
-+ MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
-+ MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
-+ MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
-+ MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
-+ MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
-+ MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
-+ MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
-+ MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
-+ MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
-+ MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
-+ MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
-+ MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
-+ MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
-+ MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
-+ MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\
-+ MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
-+ MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
-+ MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
-+ MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
-+ MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\
-+ MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\
-+ MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\
-+ MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\
-+ MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\
-+ MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\
-+ MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\
-+ MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
-+ MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
-+ MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
-+ MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
-+ MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\
-+ MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
-+ MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\
-+ MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\
-+ MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack */\
-+ MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
-+ MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
-+ MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
-+ MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
-+ MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\
-+ MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */\
-+ MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\
-+ MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used */
-+
-+/**********************************************************
-+ * Routine: set_muxconf_regs
-+ * Description: Setting up the configuration Mux registers
-+ * specific to the hardware. Many pins need
-+ * to be moved from protect to primary mode.
-+ *********************************************************/
-+void set_muxconf_regs(void)
-+{
-+ MUX_DEFAULT_ES2();
-+}
-+
-+/******************************************************************************
-+ * Routine: update_mux()
-+ * Description:Update balls which are different between boards. All should be
-+ * updated to match functionality. However, I'm only updating ones
-+ * which I'll be using for now. When power comes into play they
-+ * all need updating.
-+ *****************************************************************************/
-+void update_mux(u32 btype, u32 mtype)
-+{
-+ /* NOTHING as of now... */
-+}
-+
-+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
-+/**********************************************************
-+ * Routine: nand+_init
-+ * Description: Set up nand for nand and jffs2 commands
-+ *********************************************************/
-+void nand_init(void)
-+{
-+ extern flash_info_t flash_info[];
-+
-+ nand_probe(CFG_NAND_ADDR);
-+ if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-+ print_size(nand_dev_desc[0].totlen, "\n");
-+ }
-+#ifdef CFG_JFFS2_MEM_NAND
-+ flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
-+ /* only read kernel single meg partition */
-+ flash_info[CFG_JFFS2_FIRST_BANK].size = 1024 * 1024 * 2;
-+ /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
-+ flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024;
-+ /* ?, ram for now, open question, copy to RAM or adapt for NAND */
-+ flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000;
-+#endif
-+}
-+#endif
-diff --git a/board/omap3530beagle/sys_info.c b/board/omap3530beagle/sys_info.c
-new file mode 100644
-index 0000000..017bfaa
---- /dev/null
-+++ b/board/omap3530beagle/sys_info.c
-@@ -0,0 +1,315 @@
-+/*
-+ * (C) Copyright 2008
-+ * Texas Instruments, <www.ti.com>
-+ *
-+ * Derived from Beagle Board and 3430 SDP code by
-+ * Richard Woodruff <r-woodruff2@ti.com>
-+ * Syed Mohammed Khasim <khasim@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * (C) Copyright 2008
++ * Texas Instruments, <www.ti.com>
++ *
++ * Derived from Beagle Board and 3430 SDP code by
++ * Richard Woodruff <r-woodruff2@ti.com>
++ * Syed Mohammed Khasim <khasim@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
+ */
+
+#include <common.h>
-+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h> /* get mem tables */
+#include <asm/arch/sys_proto.h>
-+#include <asm/arch/sys_info.h>
+#include <i2c.h>
+
+/**************************************************************************
-+ * get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch
-+ * settings
-+ * 1 is on
-+ * 0 is off
-+ * Will return Index of type of gpmc
++ * get_gpmc0_type()
+ ***************************************************************************/
+u32 get_gpmc0_type(void)
+{
-+ // Default NAND
++ /* Default NAND */
+ return (2);
+}
+
+ ****************************************************/
+u32 get_cpu_type(void)
+{
-+ // fixme, need to get register defines for OMAP3
++ /* fixme, need to get register defines for OMAP3 */
+ return (CPU_3430);
+}
+
+}
diff --git a/board/omap3530beagle/syslib.c b/board/omap3530beagle/syslib.c
new file mode 100644
-index 0000000..1eb5d95
+index 0000000..002c6e8
--- /dev/null
+++ b/board/omap3530beagle/syslib.c
-@@ -0,0 +1,74 @@
+@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ */
+
+#include <common.h>
-+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
-+#include <asm/arch/sys_info.h>
+
+/************************************************************
+ * sdelay() - simple spin loop. Will be constant time as
+ .bss : { *(.bss) }
+ _end = .;
+}
+diff --git a/common/env_nand.c b/common/env_nand.c
+index a48e98e..8b04a01 100644
+--- a/common/env_nand.c
++++ b/common/env_nand.c
+@@ -231,6 +231,8 @@ int saveenv(void)
+ size_t total;
+ int ret = 0;
+
++ nand_erase_options_t nand_erase_options;
++
+ nand_erase_options.length = CFG_ENV_RANGE;
+ nand_erase_options.quiet = 0;
+ nand_erase_options.jffs2 = 0;
diff --git a/cpu/omap3/Makefile b/cpu/omap3/Makefile
new file mode 100644
index 0000000..097447a
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/omap3/cpu.c b/cpu/omap3/cpu.c
new file mode 100644
-index 0000000..d32a8cb
+index 0000000..59e6a58
--- /dev/null
+++ b/cpu/omap3/cpu.c
-@@ -0,0 +1,235 @@
+@@ -0,0 +1,221 @@
+/*
+ * (C) Copyright 2008 Texas Insturments
+ *
+#include <common.h>
+#include <command.h>
+#include <asm/arch/sys_proto.h>
-+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
-+#include <asm/arch/cpu.h>
-+#endif
-+#include <asm/arch/sys_info.h>
+
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+{
+ unsigned long value;
+
-+ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0 @ read control reg\n":"=r"(value)
++ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\
++ @ read control reg\n":"=r"(value)
+ ::"memory");
+ return value;
+}
+/* write to co-processor 15, register #1 (control register) */
+static void write_p15_c1(unsigned long value)
+{
-+ __asm__
-+ __volatile__
-+ ("mcr p15, 0, %0, c1, c0, 0 @ write it back\n"::"r"(value)
-+ : "memory");
++ __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\
++ @ write it back\n"::"r"(value)
++ : "memory");
+
+ read_p15_c1();
+}
+
+int cleanup_before_linux(void)
+{
++ unsigned int i;
++
+ /*
+ * this function is called just before we call linux
+ * it prepares the processor for linux
+ */
+ disable_interrupts();
+
-+#ifdef CONFIG_LCD
-+ {
-+ extern void lcd_disable(void);
-+ extern void lcd_panel_disable(void);
-+
-+ lcd_disable(); /* proper disable of lcd & panel */
-+ lcd_panel_disable();
-+ }
-+#endif
-+
-+ {
-+ unsigned int i;
-+
-+ /* turn off I/D-cache */
-+ asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i));
-+ i &= ~(C1_DC | C1_IC);
-+ asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i));
++ /* turn off I/D-cache */
++ asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i));
++ i &= ~(C1_DC | C1_IC);
++ asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i));
+
-+ /* invalidate I-cache */
-+ arm_cache_flush();
++ /* invalidate I-cache */
++ arm_cache_flush();
+#ifndef CONFIG_L2_OFF
-+ /* turn off L2 cache */
-+ l2cache_disable();
-+ /* invalidate L2 cache also */
-+ v7_flush_dcache_all(get_device_type());
++ /* turn off L2 cache */
++ l2cache_disable();
++ /* invalidate L2 cache also */
++ v7_flush_dcache_all(get_device_type());
+#endif
-+ i = 0;
-+ /* mem barrier to sync up things */
-+ asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
++ i = 0;
++ /* mem barrier to sync up things */
++ asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
+
+#ifndef CONFIG_L2_OFF
+ l2cache_enable();
+#endif
-+ }
+
+ return (0);
+}
+
-+int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
++int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ disable_interrupts();
+ reset_cpu(0);
-+ /*NOTREACHED*/ return (0);
++
++ /* NOTREACHED */
++ return (0);
+}
+
+void icache_enable(void)
+}
diff --git a/cpu/omap3/interrupts.c b/cpu/omap3/interrupts.c
new file mode 100644
-index 0000000..007193a
+index 0000000..818b833
--- /dev/null
+++ b/cpu/omap3/interrupts.c
-@@ -0,0 +1,299 @@
+@@ -0,0 +1,304 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments
+#include <common.h>
+#include <asm/arch/bits.h>
+
-+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
-+# include <asm/arch/cpu.h>
-+#endif
-+
+#include <asm/proc-armv/ptrace.h>
+
+#define TIMER_LOAD_VAL 0
+ bad_mode();
+}
+
-+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
-+/* Use the IntegratorCP function from board/integratorcp.c */
-+#else
+
+static ulong timestamp;
+static ulong lastinc;
+ int32_t val;
+
+ /* Start the counter ticking up */
-+ *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow */
-+ val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer */
++ /* reload value on overflow */
++ *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;
++ /* mask to enable timer */
++ val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0;
+ *((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */
+
+ reset_timer_masked(); /* init the timestamp and lastinc value */
+{
+ ulong tmo, tmp;
+
-+ if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
-+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
-+ tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
++ /* if "big" number, spread normalization to seconds */
++ if (usec >= 1000) {
++ /* if "big" number, spread normalization to seconds */
++ tmo = usec / 1000;
++ /* find number of "ticks" to wait to achieve target */
++ tmo *= CFG_HZ;
+ tmo /= 1000; /* finish normalize. */
-+ } else { /* else small number, don't kill it prior to HZ multiply */
++ } else {/* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000 * 1000);
+ }
+
+ tmp = get_timer(0); /* get current timestamp */
-+ if ((tmo + tmp + 1) < tmp) /* if setting this forward will roll time stamp */
-+ reset_timer_masked(); /* reset "advancing" timestamp to 0, set lastinc value */
++ /* if setting this forward will roll time stamp */
++ if ((tmo + tmp + 1) < tmp)
++ /* reset "advancing" timestamp to 0, set lastinc value */
++ reset_timer_masked();
+ else
+ tmo += tmp; /* else, set advancing stamp wake up time */
+ while (get_timer_masked() < tmo) /* loop till event */
+ ulong now = READ_TIMER; /* current tick value */
+
+ if (now >= lastinc) /* normal mode (non roll) */
-+ timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */
-+ else /* we have rollover of incrementer */
++ /* move stamp fordward with absoulte diff ticks */
++ timestamp += (now - lastinc);
++ else /* we have rollover of incrementer */
+ timestamp += (0xFFFFFFFF - lastinc) + now;
+ lastinc = now;
+ return timestamp;
+ ulong endtime;
+ signed long diff;
+
-+ if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
-+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
-+ tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
++ /* if "big" number, spread normalization to seconds */
++ if (usec >= 1000) {
++ /* start to normalize for usec to ticks per sec */
++ tmo = usec / 1000;
++ /* find number of "ticks" to wait to achieve target */
++ tmo *= CFG_HZ;
+ tmo /= 1000; /* finish normalize. */
-+ } else { /* else small number, don't kill it prior to HZ multiply */
++ } else { /* else small number, */
++ /* don't kill it prior to HZ multiply */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000 * 1000);
+ }
+ tbclk = CFG_HZ;
+ return tbclk;
+}
-+#endif /* !Integrator/CP */
++
diff --git a/cpu/omap3/mmc.c b/cpu/omap3/mmc.c
new file mode 100644
-index 0000000..ff6a50d
+index 0000000..741360b
--- /dev/null
+++ b/cpu/omap3/mmc.c
-@@ -0,0 +1,551 @@
+@@ -0,0 +1,559 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+
+#include <config.h>
+#include <common.h>
++#include <fat.h>
+#include <mmc.h>
+#include <part.h>
+#include <i2c.h>
-+#include "mmc_host_def.h"
-+#include "mmc_protocol.h"
+
-+extern int fat_register_device(block_dev_desc_t * dev_desc, int part_no);
++const unsigned short mmc_transspeed_val[15][4] = {
++ {CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)},
++ {CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)},
++ {CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)},
++ {CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)},
++ {CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)},
++ {CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)},
++ {CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)},
++ {CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)},
++ {CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)},
++ {CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)},
++ {CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)},
++ {CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)},
++ {CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)},
++ {CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)},
++ {CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)}
++};
+
+mmc_card_data cur_card_data;
+static block_dev_desc_t mmc_blk_dev;
+
+block_dev_desc_t *mmc_get_dev(int dev)
+{
-+ return ((block_dev_desc_t *) & mmc_blk_dev);
++ return ((block_dev_desc_t *) &mmc_blk_dev);
+}
+
+void twl4030_mmc_config(void)
+void mmc_init_stream(void)
+{
+ volatile unsigned int mmc_stat;
-+
++
+ OMAP_HSMMC_CON |= INIT_INITSTREAM;
+
+ OMAP_HSMMC_CMD = MMC_CMD0;
+ mmc_stat = OMAP_HSMMC_STAT;
+ } while (mmc_stat == 0);
+
-+ if ((mmc_stat & ERRI_MASK) != 0) {
++ if ((mmc_stat & ERRI_MASK) != 0)
+ return (unsigned char) mmc_stat;
-+ }
+
+ if (mmc_stat & CC_MASK) {
+ OMAP_HSMMC_STAT = CC_MASK;
+ return 1;
+}
+
-+unsigned char mmc_detect_card(mmc_card_data * mmc_card_cur)
++unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur)
+{
+ unsigned char err;
+ unsigned int argument = 0;
+
+ argument = ocr_value;
+ err = mmc_send_cmd(ret_cmd41, argument, resp);
-+ if (err != 1) {
++ if (err != 1)
+ return err;
-+ }
++
+ ocr_recvd = ((mmc_resp_r3 *) resp)->ocr;
+
+ while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) {
+ return 1;
+}
+
-+unsigned char mmc_read_cardsize(mmc_card_data * mmc_dev_data,
-+ mmc_csd_reg_t * cur_csd)
++unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data,
++ mmc_csd_reg_t *cur_csd)
+{
+ mmc_extended_csd_reg_t ext_csd;
+ unsigned int size, count, blk_len, blk_no, card_size, argument;
+}
+
+unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes,
-+ mmc_card_data * mmc_c,
++ mmc_card_data *mmc_c,
+ unsigned long *output_buf)
+{
+ unsigned char err;
+
+ while (num_sec_val) {
+ err = mmc_send_cmd(MMC_CMD17, argument, resp);
-+ if (err != 1) {
++ if (err != 1)
+ return err;
-+ }
+
+ err = mmc_read_data((unsigned int *) output_buf);
-+ if (err != 1) {
++ if (err != 1)
+ return err;
-+ }
++
+ output_buf += (MMCSD_SECTOR_SIZE / 4);
+ argument += sec_inc_val;
+ num_sec_val--;
+ return 1;
+}
+
-+unsigned char configure_mmc(mmc_card_data * mmc_card_cur)
++unsigned char configure_mmc(mmc_card_data *mmc_card_cur)
+{
+ unsigned char ret_val;
+ unsigned int argument;
+
+ ret_val = mmc_init_setup();
+
-+ if (ret_val != 1) {
++ if (ret_val != 1)
+ return ret_val;
-+ }
+
+ do {
+ ret_val = mmc_detect_card(mmc_card_cur);
+ ((unsigned int *) &Card_CSD)[1] = resp[1];
+ ((unsigned int *) &Card_CSD)[0] = resp[0];
+
-+ if (mmc_card_cur->card_type == MMC_CARD) {
++ if (mmc_card_cur->card_type == MMC_CARD)
+ mmc_card_cur->version = Card_CSD.spec_vers;
-+ }
+
+ trans_speed = Card_CSD.tran_speed;
+
+ return 0;
+}
+
-+int mmc_read(ulong src, uchar * dst, int size)
++int mmc_read(ulong src, uchar *dst, int size)
+{
-+ /* not implemented */
-+ return (0);
++ return 0;
+}
+
-+int mmc_write(uchar * src, ulong dst, int size)
++int mmc_write(uchar *src, ulong dst, int size)
+{
-+ /* not implementd */
-+ return (0);
++ return 0;
+}
+
+int mmc2info(ulong addr)
+{
-+ /*not implemented */
-+ return (0);
++ return 0;
+}
-diff --git a/cpu/omap3/mmc_host_def.h b/cpu/omap3/mmc_host_def.h
+diff --git a/cpu/omap3/start.S b/cpu/omap3/start.S
new file mode 100644
-index 0000000..3a84f16
+index 0000000..98706ad
--- /dev/null
-+++ b/cpu/omap3/mmc_host_def.h
-@@ -0,0 +1,164 @@
++++ b/cpu/omap3/start.S
+@@ -0,0 +1,517 @@
+/*
-+ * (C) Copyright 2008
-+ * Texas Instruments, <www.ti.com>
-+ * Syed Mohammed Khasim <khasim@ti.com>
++ * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
++ *
++ * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
++ *
++ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
++ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
++ * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
++ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
++ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
++ * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation's version 2 of
-+ * the License.
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * MA 02111-1307 USA
+ */
+
-+#ifndef MMC_HOST_DEFINITIONS_H
-+#define MMC_HOST_DEFINITIONS_H
++#include <config.h>
++#include <version.h>
+
-+/*
-+ * OMAP HSMMC register definitions
-+ */
-+#define OMAP_HSMMC_SYSCONFIG (*(unsigned int *) 0x4809C010)
-+#define OMAP_HSMMC_SYSSTATUS (*(unsigned int *) 0x4809C014)
-+#define OMAP_HSMMC_CON (*(unsigned int *) 0x4809C02C)
-+#define OMAP_HSMMC_BLK (*(unsigned int *) 0x4809C104)
-+#define OMAP_HSMMC_ARG (*(unsigned int *) 0x4809C108)
-+#define OMAP_HSMMC_CMD (*(unsigned int *) 0x4809C10C)
-+#define OMAP_HSMMC_RSP10 (*(unsigned int *) 0x4809C110)
-+#define OMAP_HSMMC_RSP32 (*(unsigned int *) 0x4809C114)
-+#define OMAP_HSMMC_RSP54 (*(unsigned int *) 0x4809C118)
-+#define OMAP_HSMMC_RSP76 (*(unsigned int *) 0x4809C11C)
-+#define OMAP_HSMMC_DATA (*(unsigned int *) 0x4809C120)
-+#define OMAP_HSMMC_PSTATE (*(unsigned int *) 0x4809C124)
-+#define OMAP_HSMMC_HCTL (*(unsigned int *) 0x4809C128)
-+#define OMAP_HSMMC_SYSCTL (*(unsigned int *) 0x4809C12C)
-+#define OMAP_HSMMC_STAT (*(unsigned int *) 0x4809C130)
-+#define OMAP_HSMMC_IE (*(unsigned int *) 0x4809C134)
-+#define OMAP_HSMMC_CAPA (*(unsigned int *) 0x4809C140)
++.globl _start
++_start: b reset
++ ldr pc, _undefined_instruction
++ ldr pc, _software_interrupt
++ ldr pc, _prefetch_abort
++ ldr pc, _data_abort
++ ldr pc, _not_used
++ ldr pc, _irq
++ ldr pc, _fiq
+
-+/* T2 Register definitions */
-+#define CONTROL_DEV_CONF0 (*(unsigned int *) 0x48002274)
-+#define CONTROL_PBIAS_LITE (*(unsigned int *) 0x48002520)
++_undefined_instruction: .word undefined_instruction
++_software_interrupt: .word software_interrupt
++_prefetch_abort: .word prefetch_abort
++_data_abort: .word data_abort
++_not_used: .word not_used
++_irq: .word irq
++_fiq: .word fiq
++_pad: .word 0x12345678 /* now 16*4=64 */
++.global _end_vect
++_end_vect:
+
-+/*
-+ * OMAP HS MMC Bit definitions
++ .balignl 16,0xdeadbeef
++/*************************************************************************
++ *
++ * Startup Code (reset vector)
++ *
++ * do important init only if we don't start from memory!
++ * setup Memory and board specific bits prior to relocation.
++ * relocate armboot to ram
++ * setup stack
++ *
++ *************************************************************************/
++
++_TEXT_BASE:
++ .word TEXT_BASE
++
++.globl _armboot_start
++_armboot_start:
++ .word _start
++
++/*
++ * These are defined in the board-specific linker script.
+ */
-+#define MMC_SOFTRESET (0x1 << 1)
-+#define RESETDONE (0x1 << 0)
-+#define NOOPENDRAIN (0x0 << 0)
-+#define OPENDRAIN (0x1 << 0)
-+#define OD (0x1 << 0)
-+#define INIT_NOINIT (0x0 << 1)
-+#define INIT_INITSTREAM (0x1 << 1)
-+#define HR_NOHOSTRESP (0x0 << 2)
-+#define STR_BLOCK (0x0 << 3)
-+#define MODE_FUNC (0x0 << 4)
-+#define DW8_1_4BITMODE (0x0 << 5)
-+#define MIT_CTO (0x0 << 6)
-+#define CDP_ACTIVEHIGH (0x0 << 7)
-+#define WPP_ACTIVEHIGH (0x0 << 8)
-+#define RESERVED_MASK (0x3 << 9)
-+#define CTPL_MMC_SD (0x0 << 11)
-+#define BLEN_512BYTESLEN (0x200 << 0)
-+#define NBLK_STPCNT (0x0 << 16)
-+#define DE_DISABLE (0x0 << 0)
-+#define BCE_DISABLE (0x0 << 1)
-+#define ACEN_DISABLE (0x0 << 2)
-+#define DDIR_OFFSET (4)
-+#define DDIR_MASK (0x1 << 4)
-+#define DDIR_WRITE (0x0 << 4)
-+#define DDIR_READ (0x1 << 4)
-+#define MSBS_SGLEBLK (0x0 << 5)
-+#define RSP_TYPE_OFFSET (16)
-+#define RSP_TYPE_MASK (0x3 << 16)
-+#define RSP_TYPE_NORSP (0x0 << 16)
-+#define RSP_TYPE_LGHT136 (0x1 << 16)
-+#define RSP_TYPE_LGHT48 (0x2 << 16)
-+#define RSP_TYPE_LGHT48B (0x3 << 16)
-+#define CCCE_NOCHECK (0x0 << 19)
-+#define CCCE_CHECK (0x1 << 19)
-+#define CICE_NOCHECK (0x0 << 20)
-+#define CICE_CHECK (0x1 << 20)
-+#define DP_OFFSET (21)
-+#define DP_MASK (0x1 << 21)
-+#define DP_NO_DATA (0x0 << 21)
-+#define DP_DATA (0x1 << 21)
-+#define CMD_TYPE_NORMAL (0x0 << 22)
-+#define INDEX_OFFSET (24)
-+#define INDEX_MASK (0x3f << 24)
-+#define INDEX(i) (i << 24)
-+#define DATI_MASK (0x1 << 1)
-+#define DATI_CMDDIS (0x1 << 1)
-+#define DTW_1_BITMODE (0x0 << 1)
-+#define DTW_4_BITMODE (0x1 << 1)
-+#define SDBP_PWROFF (0x0 << 8)
-+#define SDBP_PWRON (0x1 << 8)
-+#define SDVS_1V8 (0x5 << 9)
-+#define SDVS_3V0 (0x6 << 9)
-+#define ICE_MASK (0x1 << 0)
-+#define ICE_STOP (0x0 << 0)
-+#define ICS_MASK (0x1 << 1)
-+#define ICS_NOTREADY (0x0 << 1)
-+#define ICE_OSCILLATE (0x1 << 0)
-+#define CEN_MASK (0x1 << 2)
-+#define CEN_DISABLE (0x0 << 2)
-+#define CEN_ENABLE (0x1 << 2)
-+#define CLKD_OFFSET (6)
-+#define CLKD_MASK (0x3FF << 6)
-+#define DTO_MASK (0xF << 16)
-+#define DTO_15THDTO (0xE << 16)
-+#define SOFTRESETALL (0x1 << 24)
-+#define CC_MASK (0x1 << 0)
-+#define TC_MASK (0x1 << 1)
-+#define BWR_MASK (0x1 << 4)
-+#define BRR_MASK (0x1 << 5)
-+#define ERRI_MASK (0x1 << 15)
-+#define IE_CC (0x01 << 0)
-+#define IE_TC (0x01 << 1)
-+#define IE_BWR (0x01 << 4)
-+#define IE_BRR (0x01 << 5)
-+#define IE_CTO (0x01 << 16)
-+#define IE_CCRC (0x01 << 17)
-+#define IE_CEB (0x01 << 18)
-+#define IE_CIE (0x01 << 19)
-+#define IE_DTO (0x01 << 20)
-+#define IE_DCRC (0x01 << 21)
-+#define IE_DEB (0x01 << 22)
-+#define IE_CERR (0x01 << 28)
-+#define IE_BADA (0x01 << 29)
-+
-+#define VS30_3V0SUP (1 << 25)
-+#define VS18_1V8SUP (1 << 26)
++.globl _bss_start
++_bss_start:
++ .word __bss_start
+
-+/* Driver definitions */
-+#define MMCSD_SECTOR_SIZE (512)
-+#define MMC_CARD 0
-+#define SD_CARD 1
-+#define BYTE_MODE 0
-+#define SECTOR_MODE 1
-+#define CLK_INITSEQ 0
-+#define CLK_400KHZ 1
-+#define CLK_MISC 2
++.globl _bss_end
++_bss_end:
++ .word _end
+
-+typedef struct {
-+ unsigned int card_type;
-+ unsigned int version;
-+ unsigned int mode;
-+ unsigned int size;
-+ unsigned int RCA;
-+} mmc_card_data;
++#ifdef CONFIG_USE_IRQ
++/* IRQ stack memory (calculated at run-time) */
++.globl IRQ_STACK_START
++IRQ_STACK_START:
++ .word 0x0badc0de
+
-+#define mmc_reg_out(addr, mask, val) (addr) = ( ((addr)) & (~(mask)) ) | ( (val) & (mask) );
-+#define mmc_reg_out(addr, mask, val) (addr) = ( ((addr)) & (~(mask)) ) | ( (val) & (mask) );
++/* IRQ stack memory (calculated at run-time) */
++.globl FIQ_STACK_START
++FIQ_STACK_START:
++ .word 0x0badc0de
++#endif
+
-+#endif /* MMC_HOST_DEFINITIONS_H */
-diff --git a/cpu/omap3/mmc_protocol.h b/cpu/omap3/mmc_protocol.h
-new file mode 100644
-index 0000000..a8d9662
---- /dev/null
-+++ b/cpu/omap3/mmc_protocol.h
-@@ -0,0 +1,253 @@
+/*
-+ * (C) Copyright 2008
-+ * Texas Instruments, <www.ti.com>
-+ * Syed Mohammed Khasim <khasim@ti.com>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation's version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
++ * the actual reset code
+ */
+
-+#ifndef MMC_PROTOCOL_H
-+#define MMC_PROTOCOL_H
++reset:
++ /*
++ * set the cpu to SVC32 mode
++ */
++ mrs r0,cpsr
++ bic r0,r0,#0x1f
++ orr r0,r0,#0xd3
++ msr cpsr,r0
+
-+#include "mmc_host_def.h"
++#if (CONFIG_OMAP34XX)
++ /* Copy vectors to mask ROM indirect addr */
++ adr r0, _start @ r0 <- current position of code
++ add r0, r0, #4 @ skip reset vector
++ mov r2, #64 @ r2 <- size to copy
++ add r2, r0, r2 @ r2 <- source end address
++ mov r1, #SRAM_OFFSET0 @ build vect addr
++ mov r3, #SRAM_OFFSET1
++ add r1, r1, r3
++ mov r3, #SRAM_OFFSET2
++ add r1, r1, r3
++next:
++ ldmia r0!, {r3-r10} @ copy from source address [r0]
++ stmia r1!, {r3-r10} @ copy to target address [r1]
++ cmp r0, r2 @ until source end address [r2]
++ bne next @ loop until equal */
++#if !defined(CFG_NAND_BOOT) && !defined(CFG_ONENAND_BOOT)
++ /* No need to copy/exec the clock code - DPLL adjust already done
++ * in NAND/oneNAND Boot.
++ */
++ bl cpy_clk_code @ put dpll adjust code behind vectors
++#endif /* NAND Boot */
++#endif
++ /* the mask ROM code should have PLL and others stable */
++#ifndef CONFIG_SKIP_LOWLEVEL_INIT
++ bl cpu_init_crit
++#endif
+
-+/* Responses */
-+#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
-+#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
-+#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK)
-+#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK)
-+#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
-+#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
-+#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
-+#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
-+#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
++#ifndef CONFIG_SKIP_RELOCATE_UBOOT
++relocate: @ relocate U-Boot to RAM
++ adr r0, _start @ r0 <- current position of code
++ ldr r1, _TEXT_BASE @ test if we run from flash or RAM
++ cmp r0, r1 @ don't reloc during debug
++ beq stack_setup
+
-+/* All supported commands */
-+#define MMC_CMD0 ( INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD1 ( INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD2 ( INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD3 ( INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_SDCMD3 ( INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD4 ( INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD6 ( INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD7_SELECT ( INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD7_DESELECT ( INDEX(7) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD8 ( INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
-+#define MMC_SDCMD8 ( INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD9 ( INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD12 ( INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD13 ( INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD15 ( INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD16 ( INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_CMD17 ( INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
-+#define MMC_CMD24 ( INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE)
-+#define MMC_ACMD6 ( INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_ACMD41 ( INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
-+#define MMC_ACMD51 ( INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
-+#define MMC_CMD55 ( INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
++ ldr r2, _armboot_start
++ ldr r3, _bss_start
++ sub r2, r3, r2 @ r2 <- size of armboot
++ add r2, r0, r2 @ r2 <- source end address
+
-+#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16)
-+#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16)
-+#define MMC_DSR_DEFAULT (0x0404)
-+#define SD_CMD8_CHECK_PATTERN (0xAA)
-+#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8)
++copy_loop: @ copy 32 bytes at a time
++ ldmia r0!, {r3-r10} @ copy from source address [r0]
++ stmia r1!, {r3-r10} @ copy to target address [r1]
++ cmp r0, r2 @ until source end addreee [r2]
++ ble copy_loop
++#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
+
-+/* Clock Configurations and Macros */
++ /* Set up the stack */
++stack_setup:
++ ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
++ sub r0, r0, #CFG_MALLOC_LEN @ malloc area
++ sub r0, r0, #CFG_GBL_DATA_SIZE @ bdinfo
++#ifdef CONFIG_USE_IRQ
++ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
++#endif
++ sub sp, r0, #12 @ leave 3 words for abort-stack
++ and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d
+
-+#define MMC_CLOCK_REFERENCE (96)
-+#define MMC_RELATIVE_CARD_ADDRESS (0x1234)
-+#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80)
-+#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400)
-+#define CLKDR(r,f,u) ( ( ((r)*100) / ((f)*(u)) ) + 1 )
-+#define CLKD(f,u) (CLKDR(MMC_CLOCK_REFERENCE,f,u))
++ /* Clear BSS (if any). Is below tx (watch load addr - need space) */
++clear_bss:
++ ldr r0, _bss_start @ find start of bss segment
++ ldr r1, _bss_end @ stop here
++ mov r2, #0x00000000 @ clear value
++clbss_l:
++ str r2, [r0] @ clear BSS location
++ cmp r0, r1 @ are we at the end yet
++ add r0, r0, #4 @ increment clear index pointer
++ bne clbss_l @ keep clearing till at end
+
-+#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29)
-+#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29)
-+#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29)
++ ldr pc, _start_armboot @ jump to C code
+
-+#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30)
-+#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30)
-+#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30)
++_start_armboot: .word start_armboot
+
-+#define MMC_SD2_CSD_C_SIZE_LSB_MASK (0xFFFF)
-+#define MMC_SD2_CSD_C_SIZE_MSB_MASK (0x003F)
-+#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET (16)
-+#define MMC_CSD_C_SIZE_LSB_MASK (0x0003)
-+#define MMC_CSD_C_SIZE_MSB_MASK (0x03FF)
-+#define MMC_CSD_C_SIZE_MSB_OFFSET (2)
+
-+#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0)
-+#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3)
-+#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0)
-+#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3)
-+#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3)
++/*************************************************************************
++ *
++ * CPU_init_critical registers
++ *
++ * setup important registers
++ * setup memory timing
++ *
++ *************************************************************************/
++cpu_init_crit:
++ /*
++ * Invalidate L1 I/D
++ */
++ mov r0, #0 @ set up for MCR
++ mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
++ mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
+
-+const unsigned short mmc_transspeed_val[15][4] = {
-+ {CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)},
-+ {CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)},
-+ {CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)},
-+ {CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)},
-+ {CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)},
-+ {CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)},
-+ {CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)},
-+ {CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)},
-+ {CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)},
-+ {CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)},
-+ {CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)},
-+ {CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)},
-+ {CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)},
-+ {CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)},
-+ {CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)}
-+};
++ /*
++ * disable MMU stuff and caches
++ */
++ mrc p15, 0, r0, c1, c0, 0
++ bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
++ bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
++ orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
++ orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
++ mcr p15, 0, r0, c1, c0, 0
+
-+typedef struct {
-+ unsigned not_used:1;
-+ unsigned crc:7;
-+ unsigned ecc:2;
-+ unsigned file_format:2;
-+ unsigned tmp_write_protect:1;
-+ unsigned perm_write_protect:1;
-+ unsigned copy:1;
-+ unsigned file_format_grp:1;
-+ unsigned content_prot_app:1;
-+ unsigned reserved_1:4;
-+ unsigned write_bl_partial:1;
-+ unsigned write_bl_len:4;
-+ unsigned r2w_factor:3;
-+ unsigned default_ecc:2;
-+ unsigned wp_grp_enable:1;
-+ unsigned wp_grp_size:5;
-+ unsigned erase_grp_mult:5;
-+ unsigned erase_grp_size:5;
-+ unsigned c_size_mult:3;
-+ unsigned vdd_w_curr_max:3;
-+ unsigned vdd_w_curr_min:3;
-+ unsigned vdd_r_curr_max:3;
-+ unsigned vdd_r_curr_min:3;
-+ unsigned c_size_lsb:2;
-+ unsigned c_size_msb:10;
-+ unsigned reserved_2:2;
-+ unsigned dsr_imp:1;
-+ unsigned read_blk_misalign:1;
-+ unsigned write_blk_misalign:1;
-+ unsigned read_bl_partial:1;
-+ unsigned read_bl_len:4;
-+ unsigned ccc:12;
-+ unsigned tran_speed:8;
-+ unsigned nsac:8;
-+ unsigned taac:8;
-+ unsigned reserved_3:2;
-+ unsigned spec_vers:4;
-+ unsigned csd_structure:2;
-+} mmc_csd_reg_t;
-+
-+/* csd for sd2.0 */
-+typedef struct {
-+ unsigned not_used:1;
-+ unsigned crc:7;
-+ unsigned reserved_1:2;
-+ unsigned file_format:2;
-+ unsigned tmp_write_protect:1;
-+ unsigned perm_write_protect:1;
-+ unsigned copy:1;
-+ unsigned file_format_grp:1;
-+ unsigned reserved_2:5;
-+ unsigned write_bl_partial:1;
-+ unsigned write_bl_len:4;
-+ unsigned r2w_factor:3;
-+ unsigned reserved_3:2;
-+ unsigned wp_grp_enable:1;
-+ unsigned wp_grp_size:7;
-+ unsigned sector_size:7;
-+ unsigned erase_blk_len:1;
-+ unsigned reserved_4:1;
-+ unsigned c_size_lsb:16;
-+ unsigned c_size_msb:6;
-+ unsigned reserved_5:6;
-+ unsigned dsr_imp:1;
-+ unsigned read_blk_misalign:1;
-+ unsigned write_blk_misalign:1;
-+ unsigned read_bl_partial:1;
-+ unsigned read_bl_len:4;
-+ unsigned ccc:12;
-+ unsigned tran_speed:8;
-+ unsigned nsac:8;
-+ unsigned taac:8;
-+ unsigned reserved_6:6;
-+ unsigned csd_structure:2;
-+} mmc_sd2_csd_reg_t;
-+
-+/* extended csd - 512 bytes long */
-+typedef struct {
-+ unsigned char reserved_1[181];
-+ unsigned char erasedmemorycontent;
-+ unsigned char reserved_2;
-+ unsigned char buswidthmode;
-+ unsigned char reserved_3;
-+ unsigned char highspeedinterfacetiming;
-+ unsigned char reserved_4;
-+ unsigned char powerclass;
-+ unsigned char reserved_5;
-+ unsigned char commandsetrevision;
-+ unsigned char reserved_6;
-+ unsigned char commandset;
-+ unsigned char extendedcsdrevision;
-+ unsigned char reserved_7;
-+ unsigned char csdstructureversion;
-+ unsigned char reserved_8;
-+ unsigned char cardtype;
-+ unsigned char reserved_9[3];
-+ unsigned char powerclass_52mhz_1_95v;
-+ unsigned char powerclass_26mhz_1_95v;
-+ unsigned char powerclass_52mhz_3_6v;
-+ unsigned char powerclass_26mhz_3_6v;
-+ unsigned char reserved_10;
-+ unsigned char minreadperf_4b_26mhz;
-+ unsigned char minwriteperf_4b_26mhz;
-+ unsigned char minreadperf_8b_26mhz_4b_52mhz;
-+ unsigned char minwriteperf_8b_26mhz_4b_52mhz;
-+ unsigned char minreadperf_8b_52mhz;
-+ unsigned char minwriteperf_8b_52mhz;
-+ unsigned char reserved_11;
-+ unsigned int sectorcount;
-+ unsigned char reserved_12[288];
-+ unsigned char supportedcommandsets;
-+ unsigned char reserved_13[7];
-+} mmc_extended_csd_reg_t;
-+
-+/* mmc sd responce */
-+typedef struct {
-+ unsigned int ocr;
-+} mmc_resp_r3;
-+
-+typedef struct {
-+ unsigned short cardstatus;
-+ unsigned short newpublishedrca;
-+} mmc_resp_r6;
-+
-+extern mmc_card_data mmc_dev;
-+
-+unsigned char mmc_lowlevel_init(void);
-+unsigned char mmc_send_command(unsigned int cmd, unsigned int arg,
-+ unsigned int *response);
-+unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd);
-+unsigned char mmc_set_opendrain(unsigned char state);
-+unsigned char mmc_read_data(unsigned int *output_buf);
-+
-+#endif /*MMC_PROTOCOL_H */
-diff --git a/cpu/omap3/start.S b/cpu/omap3/start.S
-new file mode 100644
-index 0000000..065b3c7
---- /dev/null
-+++ b/cpu/omap3/start.S
-@@ -0,0 +1,484 @@
-+/*
-+ * armboot - Startup Code for OMAP3430/ARM Cortex CPU-core
-+ *
-+ * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
-+ *
-+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
-+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
-+ * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
-+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
-+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
-+ * Copyright (c) 2006 Syed Mohammed Khasim <x0khasim@ti.com>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <config.h>
-+#include <version.h>
-+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
-+#include <asm/arch/cpu.h>
-+#endif
-+.globl _start
-+_start: b reset
-+ ldr pc, _undefined_instruction
-+ ldr pc, _software_interrupt
-+ ldr pc, _prefetch_abort
-+ ldr pc, _data_abort
-+ ldr pc, _not_used
-+ ldr pc, _irq
-+ ldr pc, _fiq
-+
-+_undefined_instruction: .word undefined_instruction
-+_software_interrupt: .word software_interrupt
-+_prefetch_abort: .word prefetch_abort
-+_data_abort: .word data_abort
-+_not_used: .word not_used
-+_irq: .word irq
-+_fiq: .word fiq
-+_pad: .word 0x12345678 /* now 16*4=64 */
-+.global _end_vect
-+_end_vect:
-+
-+ .balignl 16,0xdeadbeef
-+/*
-+ *************************************************************************
-+ *
-+ * Startup Code (reset vector)
-+ *
-+ * do important init only if we don't start from memory!
-+ * setup Memory and board specific bits prior to relocation.
-+ * relocate armboot to ram
-+ * setup stack
-+ *
-+ *************************************************************************
-+ */
-+
-+_TEXT_BASE:
-+ .word TEXT_BASE
-+
-+.globl _armboot_start
-+_armboot_start:
-+ .word _start
-+
-+/*
-+ * These are defined in the board-specific linker script.
-+ */
-+.globl _bss_start
-+_bss_start:
-+ .word __bss_start
-+
-+.globl _bss_end
-+_bss_end:
-+ .word _end
-+
-+#ifdef CONFIG_USE_IRQ
-+/* IRQ stack memory (calculated at run-time) */
-+.globl IRQ_STACK_START
-+IRQ_STACK_START:
-+ .word 0x0badc0de
-+
-+/* IRQ stack memory (calculated at run-time) */
-+.globl FIQ_STACK_START
-+FIQ_STACK_START:
-+ .word 0x0badc0de
-+#endif
-+
-+/*
-+ * the actual reset code
-+ */
-+
-+reset:
+ /*
-+ * set the cpu to SVC32 mode
++ * Jump to board specific initialization...
++ * The Mask ROM will have already initialized
++ * basic memory. Go here to bump up clock rate and handle
++ * wake up conditions.
+ */
-+ mrs r0,cpsr
-+ bic r0,r0,#0x1f
-+ orr r0,r0,#0xd3
-+ msr cpsr,r0
-+
-+#if (CONFIG_OMAP34XX)
-+ /* Copy vectors to mask ROM indirect addr */
-+ adr r0, _start /* r0 <- current position of code */
-+ add r0, r0, #4 /* skip reset vector */
-+ mov r2, #64 /* r2 <- size to copy */
-+ add r2, r0, r2 /* r2 <- source end address */
-+ mov r1, #SRAM_OFFSET0 /* build vect addr */
-+ mov r3, #SRAM_OFFSET1
-+ add r1, r1, r3
-+ mov r3, #SRAM_OFFSET2
-+ add r1, r1, r3
-+next:
-+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
-+ stmia r1!, {r3-r10} /* copy to target address [r1] */
-+ cmp r0, r2 /* until source end address [r2] */
-+ bne next /* loop until equal */
-+#if !defined(CFG_NAND_BOOT) && !defined(CFG_ONENAND_BOOT)
-+ /* No need to copy/exec the clock code - DPLL adjust already done
-+ * in NAND/oneNAND Boot.
-+ */
-+ bl cpy_clk_code /* put dpll adjust code behind vectors */
-+#endif /* NAND Boot */
-+#endif /* 24xx */
-+ /* the mask ROM code should have PLL and others stable */
-+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-+ bl cpu_init_crit
-+#endif
-+
-+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-+relocate: /* relocate U-Boot to RAM */
-+ adr r0, _start /* r0 <- current position of code */
-+ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
-+ cmp r0, r1 /* don't reloc during debug */
-+ beq stack_setup
-+
-+ ldr r2, _armboot_start
-+ ldr r3, _bss_start
-+ sub r2, r3, r2 /* r2 <- size of armboot */
-+ add r2, r0, r2 /* r2 <- source end address */
-+
-+copy_loop: /* copy 32 bytes at a time */
-+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
-+ stmia r1!, {r3-r10} /* copy to target address [r1] */
-+ cmp r0, r2 /* until source end addreee [r2] */
-+ ble copy_loop
-+#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-+
-+ /* Set up the stack */
-+stack_setup:
-+ ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
-+ sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
-+ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
-+#ifdef CONFIG_USE_IRQ
-+ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-+#endif
-+ sub sp, r0, #12 /* leave 3 words for abort-stack */
-+ and sp, sp, #~7 /* 8 byte alinged for (ldr/str)d */
-+
-+ /* Clear BSS (if any). Is below tx (watch load addr - need space) */
-+clear_bss:
-+ ldr r0, _bss_start /* find start of bss segment */
-+ ldr r1, _bss_end /* stop here */
-+ mov r2, #0x00000000 /* clear value */
-+clbss_l:
-+ str r2, [r0] /* clear BSS location */
-+ cmp r0, r1 /* are we at the end yet */
-+ add r0, r0, #4 /* increment clear index pointer */
-+ bne clbss_l /* keep clearing till at end */
-+
-+ ldr pc, _start_armboot /* jump to C code */
-+
-+_start_armboot: .word start_armboot
-+
-+
-+/*
-+ *************************************************************************
-+ *
-+ * CPU_init_critical registers
-+ *
-+ * setup important registers
-+ * setup memory timing
-+ *
-+ *************************************************************************
-+ */
-+cpu_init_crit:
-+ /*
-+ * Invalidate L1 I/D
-+ */
-+ mov r0, #0 /* set up for MCR */
-+ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
-+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
-+
-+ /*
-+ * disable MMU stuff and caches
-+ */
-+ mrc p15, 0, r0, c1, c0, 0
-+ bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
-+ bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
-+ orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
-+ orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
-+ mcr p15, 0, r0, c1, c0, 0
-+
-+ /*
-+ * Jump to board specific initialization... The Mask ROM will have already initialized
-+ * basic memory. Go here to bump up clock rate and handle wake up conditions.
-+ */
-+ mov ip, lr /* persevere link reg across call */
-+ bl lowlevel_init /* go setup pll,mux,memory */
-+ mov lr, ip /* restore link */
-+ mov pc, lr /* back to my caller */
++ mov ip, lr @ persevere link reg across call
++ bl lowlevel_init @ go setup pll,mux,memory
++ mov lr, ip @ restore link
++ mov pc, lr @ back to my caller
+/*
+ *************************************************************************
+ *
+ */
+
+ .macro bad_save_user_regs
-+ sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
-+ stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
++ sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
++ @ user stack
++ stmia sp, {r0 - r12} @ Save user registers (now in
++ @ svc mode) r0-r12
+
+ ldr r2, _armboot_start
+ sub r2, r2, #(CFG_MALLOC_LEN)
-+ sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
-+ ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
++ sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort
++ @ stack
++ ldmia r2, {r2 - r3} @ get values for "aborted" pc
++ @ and cpsr (into parm regs)
+ add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
+
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
-+ mov r0, sp @ save current stack into r0 (param register)
++ mov r0, sp @ save current stack into r0
++ @ (param register)
+ .endm
+
+ .macro irq_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
-+ add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
++ add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
++ @ a reserved stack spot would
++ @ be good.
+ stmdb r8, {sp, lr}^ @ Calling SP, LR
+ str lr, [r8, #0] @ Save calling PC
+ mrs r6, spsr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
-+ subs pc, lr, #4 @ return & move spsr_svc into cpsr
++ subs pc, lr, #4 @ return & move spsr_svc into
++ @ cpsr
+ .endm
+
+ .macro get_bad_stack
-+ ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
++ ldr r13, _armboot_start @ setup our mode stack (enter
++ @ in banked mode)
+ sub r13, r13, #(CFG_MALLOC_LEN) @ move past malloc pool
-+ sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
++ sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple
++ @ spots for abort stack
+
-+ str lr, [r13] @ save caller lr in position 0 of saved stack
++ str lr, [r13] @ save caller lr in position 0
++ @ of saved stack
+ mrs lr, spsr @ get the spsr
-+ str lr, [r13, #4] @ save spsr in position 1 of saved stack
++ str lr, [r13, #4] @ save spsr in position 1 of
++ @ saved stack
+
+ mov r13, #MODE_SVC @ prepare SVC-Mode
+ @ msr spsr_c, r13
-+ msr spsr, r13 @ switch modes, make sure moves will execute
++ msr spsr, r13 @ switch modes, make sure
++ @ moves will execute
+ mov lr, pc @ capture return pc
-+ movs pc, lr @ jump to next instruction & switch modes.
++ movs pc, lr @ jump to next instruction &
++ @ switch modes.
+ .endm
+
+ .macro get_bad_stack_swi
-+ sub r13, r13, #4 @ space on current stack for scratch reg.
++ sub r13, r13, #4 @ space on current stack for
++ @ scratch reg.
+ str r0, [r13] @ save R0's value.
+ ldr r0, _armboot_start @ get data regions start
+ sub r0, r0, #(CFG_MALLOC_LEN) @ move past malloc pool
-+ sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack
-+ str lr, [r0] @ save caller lr in position 0 of saved stack
++ sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple
++ @ spots for abort stack
++ str lr, [r0] @ save caller lr in position 0
++ @ of saved stack
+ mrs r0, spsr @ get the spsr
-+ str lr, [r0, #4] @ save spsr in position 1 of saved stack
++ str lr, [r0, #4] @ save spsr in position 1 of
++ @ saved stack
+ ldr r0, [r13] @ restore r0
+ add r13, r13, #4 @ pop stack entry
+ .endm
+ .align 5
+.global arm_cache_flush
+arm_cache_flush:
-+ mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
-+ mov pc, lr @ back to caller
++ mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
++ mov pc, lr @ back to caller
+
+/*
+ * v7_flush_dcache_all()
+ stmfd r13!, {r0-r5, r7, r9-r12,r14}
+
+ mov r7, r0 @ take a backup of device type
-+ cmp r0, #0x3 @ check if the device type is GP
-+ moveq r12, #0x1 @ set up to invalide L2
++ cmp r0, #0x3 @ check if the device type is
++ @ GP
++ moveq r12, #0x1 @ set up to invalide L2
+smi: .word 0x01600070 @ Call SMI monitor (smieq)
-+ cmp r7, #0x3 @ compare again in case its lost
-+ beq finished_inval @ if GP device, inval done above
++ cmp r7, #0x3 @ compare again in case its
++ @ lost
++ beq finished_inval @ if GP device, inval done
++ @ above
+
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ ands r3, r0, #0x7000000 @ extract loc from clidr
+ mov r3, r3, lsr #23 @ left align loc bit field
-+ beq finished_inval @ if loc is 0, then no need to clean
++ beq finished_inval @ if loc is 0, then no need to
++ @ clean
+ mov r10, #0 @ start clean at cache level 0
+inval_loop1:
-+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
-+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
-+ and r1, r1, #7 @ mask of the bits for current cache only
-+ cmp r1, #2 @ see what cache we have at this level
-+ blt skip_inval @ skip if no cache, or just i-cache
-+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
-+ isb @ isb to sych the new cssr&csidr
++ add r2, r10, r10, lsr #1 @ work out 3x current cache
++ @ level
++ mov r1, r0, lsr r2 @ extract cache type bits from
++ @ clidr
++ and r1, r1, #7 @ mask of the bits for current
++ @ cache only
++ cmp r1, #2 @ see what cache we have at
++ @ this level
++ blt skip_inval @ skip if no cache, or just
++ @ i-cache
++ mcr p15, 2, r10, c0, c0, 0 @ select current cache level
++ @ in cssr
++ isb @ isb to sych the new
++ @ cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
-+ and r2, r1, #7 @ extract the length of the cache lines
++ and r2, r1, #7 @ extract the length of the
++ @ cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ ldr r4, =0x3ff
-+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
-+ clz r5, r4 @ find bit position of way size increment
++ ands r4, r4, r1, lsr #3 @ find maximum number on the
++ @ way size
++ clz r5, r4 @ find bit position of way
++ @ size increment
+ ldr r7, =0x7fff
-+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
++ ands r7, r7, r1, lsr #13 @ extract max number of the
++ @ index size
+inval_loop2:
-+ mov r9, r4 @ create working copy of max way size
++ mov r9, r4 @ create working copy of max
++ @ way size
+inval_loop3:
-+ orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
++ orr r11, r10, r9, lsl r5 @ factor way and cache number
++ @ into r11
+ orr r11, r11, r7, lsl r2 @ factor index number into r11
+ mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
+ subs r9, r9, #1 @ decrement the way
+ bgt inval_loop1
+finished_inval:
+ mov r10, #0 @ swith back to cache level 0
-+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
++ mcr p15, 2, r10, c0, c0, 0 @ select current cache level
++ @ in cssr
+ isb
-+
++
+ ldmfd r13!, {r0-r5, r7, r9-r12,pc}
-+
++
+
+ .align 5
+.global reset_cpu
+reset_cpu:
-+ ldr r1, rstctl /* get addr for global reset reg */
-+ mov r3, #0x2 /* full reset pll+mpu */
-+ str r3, [r1] /* force reset */
++ ldr r1, rstctl @ get addr for global reset
++ @ reg
++ mov r3, #0x2 @ full reset pll + mpu
++ str r3, [r1] @ force reset
+ mov r0, r0
+_loop_forever:
+ b _loop_forever
+#endif /* endif _CLOCKS_OMAP3_H_ */
diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
new file mode 100644
-index 0000000..5bb9faa
+index 0000000..d47defb
--- /dev/null
+++ b/include/asm-arm/arch-omap3/cpu.h
-@@ -0,0 +1,245 @@
+@@ -0,0 +1,250 @@
+/*
-+ * (C) Copyright 2006
++ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ *
+ */
+
-+#ifndef _OMAP34XX_CPU_H
-+#define _OMAP34XX_CPU_H
-+#include <asm/arch/omap3.h>
++#ifndef _CPU_H
++#define _CPU_H
+
+/* Register offsets of common modules */
+/* Control */
+#define GPMC_ECC9_RESULT (0x220)
+
+/* GPMC Mapping */
-+# define FLASH_BASE 0x10000000 /* NOR flash (aligned to 256 Meg) */
-+# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (aligned to 64 Meg) */
-+# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (aligned to 256 Meg) */
++# define FLASH_BASE 0x10000000 /* NOR flash, */
++ /* aligned to 256 Meg */
++# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
++ /* aligned to 64 Meg */
++# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
++ /* aligned to 256 Meg */
+# define DEBUG_BASE 0x08000000 /* debug board */
-+# define NAND_BASE 0x30000000 /* NAND addr (actual size small port) */
++# define NAND_BASE 0x30000000 /* NAND addr */
++ /* (actual size small port) */
+# define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
-+# define ONENAND_MAP 0x20000000 /* OneNand addr (actual size small port */
++# define ONENAND_MAP 0x20000000 /* OneNand addr */
++ /* (actual size small port) */
+
+/* SMS */
+#define SMS_SYSCONFIG (OMAP34XX_SMS_BASE+0x10)
+#define TCAR1 0x3c /* r */
+#define TSICR 0x40 /* rw */
+#define TCAR2 0x44 /* r */
-+#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */
++ /* enable sys_clk NO-prescale /1 */
++#define GPT_EN ((0<<2)|BIT1|BIT0)
+
+/* Watchdog */
+#define WWPS 0x34 /* r */
+#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
+#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
+
-+#endif
++#endif /* _CPU_H */
diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch-omap3/i2c.h
new file mode 100644
-index 0000000..1b8524e
+index 0000000..5fb0979
--- /dev/null
+++ b/include/asm-arm/arch-omap3/i2c.h
-@@ -0,0 +1,130 @@
+@@ -0,0 +1,128 @@
+/*
-+ * (C) Copyright 2004-2006
++ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
-+#ifndef _OMAP34XX_I2C_H_
-+#define _OMAP34XX_I2C_H_
-+
-+/* Get the i2c base addresses */
-+#include <asm/arch/cpu.h>
++#ifndef _I2C_H_
++#define _I2C_H_
+
+#define I2C_DEFAULT_BASE I2C_BASE1
+
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_GC_IE (1 << 5)
-+#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
-+#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
-+#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
-+#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
-+#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
++#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
++#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
++#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
++#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
++#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
-+#define I2C_STAT_SBD (1 << 15) /* Single byte data */
-+#define I2C_STAT_BB (1 << 12) /* Bus busy */
-+#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
-+#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
-+#define I2C_STAT_AAS (1 << 9) /* Address as slave */
++#define I2C_STAT_SBD (1 << 15) /* Single byte data */
++#define I2C_STAT_BB (1 << 12) /* Bus busy */
++#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
++#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
++#define I2C_STAT_AAS (1 << 9) /* Address as slave */
+#define I2C_STAT_GC (1 << 5)
-+#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
-+#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
-+#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
-+#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
-+#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
++#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
++#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
++#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
++#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
++#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
-+#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
-+#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
++#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
++#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
+
+/* I2C Configuration Register (I2C_CON): */
+
-+#define I2C_CON_EN (1 << 15) /* I2C module enable */
-+#define I2C_CON_BE (1 << 14) /* Big endian mode */
-+#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
-+#define I2C_CON_MST (1 << 10) /* Master/slave mode */
-+#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
-+#define I2C_CON_XA (1 << 8) /* Expand address */
-+#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
-+#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
++#define I2C_CON_EN (1 << 15) /* I2C module enable */
++#define I2C_CON_BE (1 << 14) /* Big endian mode */
++#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
++#define I2C_CON_MST (1 << 10) /* Master/slave mode */
++#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode /*
++ /* (master mode only) */
++#define I2C_CON_XA (1 << 8) /* Expand address */
++#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
++#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
-+#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
-+#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */
-+#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
-+#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
-+#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
-+#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
-+#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
-+#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
++#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
++#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
++#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
++#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
++#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
++#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
++#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
++#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
+
+#define I2C_SCLL_SCLL (0)
+#define I2C_SCLL_SCLL_M (0xFF)
+#define I2C_SCLH_HSSCLH (8)
+#define I2C_SCLH_HSSCLH_M (0xFF)
+
-+#define OMAP_I2C_STANDARD 100
-+#define OMAP_I2C_FAST_MODE 400
-+#define OMAP_I2C_HIGH_SPEED 3400
++#define OMAP_I2C_STANDARD 100
++#define OMAP_I2C_FAST_MODE 400
++#define OMAP_I2C_HIGH_SPEED 3400
++
++#define SYSTEM_CLOCK_12 12000
++#define SYSTEM_CLOCK_13 13000
++#define SYSTEM_CLOCK_192 19200
++#define SYSTEM_CLOCK_96 96000
++
++#define I2C_IP_CLK SYSTEM_CLOCK_96
++#define I2C_PSC_MAX (0x0f)
++#define I2C_PSC_MIN (0x00)
++
++#endif /* _I2C_H_ */
+diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
+new file mode 100644
+index 0000000..2c5cc51
+--- /dev/null
++++ b/include/asm-arm/arch-omap3/mem.h
+@@ -0,0 +1,220 @@
++/*
++ * (C) Copyright 2006-2008
++ * Texas Instruments, <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef _MEM_H_
++#define _MEM_H_
++
++#define SDRC_CS0_OSET 0x0
++#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
++
++#ifndef __ASSEMBLY__
++
++typedef enum {
++ STACKED = 0,
++ IP_DDR = 1,
++ COMBO_DDR = 2,
++ IP_SDR = 3,
++} mem_t;
++
++#endif /* __ASSEMBLY__ */
++
++#define EARLY_INIT 1
++
++/* Slower full frequency range default timings for x32 operation*/
++#define SDP_SDRC_SHARING 0x00000100
++#define SDP_SDRC_MR_0_SDR 0x00000031
++
++/* optimized timings good for current shipping parts */
++#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
++
++#define DLL_OFFSET 0
++#define DLL_WRITEDDRCLKX2DIS 1
++#define DLL_ENADLL 1
++#define DLL_LOCKDLL 0
++#define DLL_DLLPHASE_72 0
++#define DLL_DLLPHASE_90 1
++
++/* rkw - need to find of 90/72 degree recommendation for speed like before */
++#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
++ (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
++
++/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
++ * ACTIMA
++ * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
++ * TDPL (Twr) = 15/6 = 2.5 -> 3
++ * TRRD = 12/6 = 2
++ * TRCD = 18/6 = 3
++ * TRP = 18/6 = 3
++ * TRAS = 42/6 = 7
++ * TRC = 60/6 = 10
++ * TRFC = 72/6 = 12
++ * ACTIMB
++ * TCKE = 2
++ * XSR = 120/6 = 20
++ */
++#define TDAL_165 6
++#define TDPL_165 3
++#define TRRD_165 2
++#define TRCD_165 3
++#define TRP_165 3
++#define TRAS_165 7
++#define TRC_165 10
++#define TRFC_165 12
++#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) \
++ | (TRP_165 << 15) | (TRCD_165 << 12) | (TRRD_165 << 9) | \
++ (TDPL_165 << 6) | (TDAL_165))
++
++#define TWTR_165 1
++#define TCKE_165 2
++#define TXP_165 2
++#define XSR_165 20
++#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
++ (TXP_165 << 8) | (TWTR_165 << 16))
++
++# define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
++# define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
++# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
++
++/*
++ * GPMC settings -
++ * Definitions is as per the following format
++ * # define <PART>_GPMC_CONFIG<x> <value>
++ * Where:
++ * PART is the part name e.g. STNOR - Intel Strata Flash
++ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
++ * Value is corresponding value
++ *
++ * For every valid PRCM configuration there should be only one definition of
++ * the same. if values are independent of the board, this definition will be
++ * present in this file if values are dependent on the board, then this should
++ * go into corresponding mem-boardName.h file
++ *
++ * Currently valid part Names are (PART):
++ * STNOR - Intel Strata Flash
++ * SMNAND - Samsung NAND
++ * MPDB - H4 MPDB board
++ * SBNOR - Sibley NOR
++ * MNAND - Micron Large page x16 NAND
++ * ONNAND - Samsung One NAND
++ *
++ * include/configs/file.h contains the defn - for all CS we are interested
++ * #define OMAP34XX_GPMC_CSx PART
++ * #define OMAP34XX_GPMC_CSx_SIZE Size
++ * #define OMAP34XX_GPMC_CSx_MAP Map
++ * Where:
++ * x - CS number
++ * PART - Part Name as defined above
++ * SIZE - how big is the mapping to be
++ * GPMC_SIZE_128M - 0x8
++ * GPMC_SIZE_64M - 0xC
++ * GPMC_SIZE_32M - 0xE
++ * GPMC_SIZE_16M - 0xF
++ * MAP - Map this CS to which address(GPMC address space)- Absolute address
++ * >>24 before being used.
++ */
++#define GPMC_SIZE_128M 0x8
++#define GPMC_SIZE_64M 0xC
++#define GPMC_SIZE_32M 0xE
++#define GPMC_SIZE_16M 0xF
++
++# define SMNAND_GPMC_CONFIG1 0x00000800
++# define SMNAND_GPMC_CONFIG2 0x00141400
++# define SMNAND_GPMC_CONFIG3 0x00141400
++# define SMNAND_GPMC_CONFIG4 0x0F010F01
++# define SMNAND_GPMC_CONFIG5 0x010C1414
++# define SMNAND_GPMC_CONFIG6 0x1F0F0A80
++# define SMNAND_GPMC_CONFIG7 0x00000C44
++
++# define M_NAND_GPMC_CONFIG1 0x00001800
++# define M_NAND_GPMC_CONFIG2 0x00141400
++# define M_NAND_GPMC_CONFIG3 0x00141400
++# define M_NAND_GPMC_CONFIG4 0x0F010F01
++# define M_NAND_GPMC_CONFIG5 0x010C1414
++# define M_NAND_GPMC_CONFIG6 0x1f0f0A80
++# define M_NAND_GPMC_CONFIG7 0x00000C44
++
++# define STNOR_GPMC_CONFIG1 0x3
++# define STNOR_GPMC_CONFIG2 0x00151501
++# define STNOR_GPMC_CONFIG3 0x00060602
++# define STNOR_GPMC_CONFIG4 0x11091109
++# define STNOR_GPMC_CONFIG5 0x01141F1F
++# define STNOR_GPMC_CONFIG6 0x000004c4
++
++# define SIBNOR_GPMC_CONFIG1 0x1200
++# define SIBNOR_GPMC_CONFIG2 0x001f1f00
++# define SIBNOR_GPMC_CONFIG3 0x00080802
++# define SIBNOR_GPMC_CONFIG4 0x1C091C09
++# define SIBNOR_GPMC_CONFIG5 0x01131F1F
++# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
++
++# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
++# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
++# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
++# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
++# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
++# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
++
++# define MPDB_GPMC_CONFIG1 0x00011000
++# define MPDB_GPMC_CONFIG2 0x001f1f01
++# define MPDB_GPMC_CONFIG3 0x00080803
++# define MPDB_GPMC_CONFIG4 0x1c0b1c0a
++# define MPDB_GPMC_CONFIG5 0x041f1F1F
++# define MPDB_GPMC_CONFIG6 0x1F0F04C4
++
++# define P2_GPMC_CONFIG1 0x0
++# define P2_GPMC_CONFIG2 0x0
++# define P2_GPMC_CONFIG3 0x0
++# define P2_GPMC_CONFIG4 0x0
++# define P2_GPMC_CONFIG5 0x0
++# define P2_GPMC_CONFIG6 0x0
++
++# define ONENAND_GPMC_CONFIG1 0x00001200
++# define ONENAND_GPMC_CONFIG2 0x000F0F01
++# define ONENAND_GPMC_CONFIG3 0x00030301
++# define ONENAND_GPMC_CONFIG4 0x0F040F04
++# define ONENAND_GPMC_CONFIG5 0x010F1010
++# define ONENAND_GPMC_CONFIG6 0x1F060000
++
++/* max number of GPMC Chip Selects */
++#define GPMC_MAX_CS 8
++/* max number of GPMC regs */
++#define GPMC_MAX_REG 7
+
-+#define SYSTEM_CLOCK_12 12000
-+#define SYSTEM_CLOCK_13 13000
-+#define SYSTEM_CLOCK_192 19200
-+#define SYSTEM_CLOCK_96 96000
++#define PISMO1_NOR 1
++#define PISMO1_NAND 2
++#define PISMO2_CS0 3
++#define PISMO2_CS1 4
++#define PISMO1_ONENAND 5
++#define DBG_MPDB 6
++#define PISMO2_NAND_CS0 7
++#define PISMO2_NAND_CS1 8
+
-+#define I2C_IP_CLK SYSTEM_CLOCK_96
-+#define I2C_PSC_MAX (0x0f)
-+#define I2C_PSC_MIN (0x00)
++/* make it readable for the gpmc_init */
++#define PISMO1_NOR_BASE FLASH_BASE
++#define PISMO1_NAND_BASE NAND_BASE
++#define PISMO2_CS0_BASE PISMO2_MAP1
++#define PISMO1_ONEN_BASE ONENAND_MAP
++#define DBG_MPDB_BASE DEBUG_BASE
+
-+#endif
-diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
++#endif /* endif _MEM_H_ */
+diff --git a/include/asm-arm/arch-omap3/mmc.h b/include/asm-arm/arch-omap3/mmc.h
new file mode 100644
-index 0000000..1af53a8
+index 0000000..8631aae
--- /dev/null
-+++ b/include/asm-arm/arch-omap3/mem.h
-@@ -0,0 +1,220 @@
++++ b/include/asm-arm/arch-omap3/mmc.h
+@@ -0,0 +1,235 @@
+/*
-+ * (C) Copyright 2006-2008
++ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
-+ * Richard Woodruff <r-woodruff2@ti.com>
++ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
++ * published by the Free Software Foundation's version 2 of
++ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MA 02111-1307 USA
+ */
+
-+#ifndef _MEM_H_
-+#define _MEM_H_
++#ifndef MMC_H
++#define MMC_H
+
-+#define SDRC_CS0_OSET 0x0
-+#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
++#include "mmc_host_def.h"
+
-+#ifndef __ASSEMBLY__
++/* Responses */
++#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
++#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
++#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK)
++#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK)
++#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
++#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
++#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
++#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
++#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
+
-+typedef enum {
-+ STACKED = 0,
-+ IP_DDR = 1,
-+ COMBO_DDR = 2,
-+ IP_SDR = 3,
-+} mem_t;
++/* All supported commands */
++#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
++#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD7_DESELECT (INDEX(7) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
++#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
++#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE)
++#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
++#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
++#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
++#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
+
-+#endif /* __ASSEMBLY__ */
++#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16)
++#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16)
++#define MMC_DSR_DEFAULT (0x0404)
++#define SD_CMD8_CHECK_PATTERN (0xAA)
++#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8)
+
-+#define EARLY_INIT 1
++/* Clock Configurations and Macros */
+
-+/* Slower full frequency range default timings for x32 operation*/
-+#define SDP_SDRC_SHARING 0x00000100
-+#define SDP_SDRC_MR_0_SDR 0x00000031
++#define MMC_CLOCK_REFERENCE (96)
++#define MMC_RELATIVE_CARD_ADDRESS (0x1234)
++#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80)
++#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400)
++#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1)
++#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u))
+
-+/* optimized timings good for current shipping parts */
-+#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
++#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29)
++#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29)
++#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29)
+
-+#define DLL_OFFSET 0
-+#define DLL_WRITEDDRCLKX2DIS 1
-+#define DLL_ENADLL 1
-+#define DLL_LOCKDLL 0
-+#define DLL_DLLPHASE_72 0
-+#define DLL_DLLPHASE_90 1
++#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30)
++#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30)
++#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30)
+
-+// rkw - need to find of 90/72 degree recommendation for speed like before.
-+#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
-+ (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
++#define MMC_SD2_CSD_C_SIZE_LSB_MASK (0xFFFF)
++#define MMC_SD2_CSD_C_SIZE_MSB_MASK (0x003F)
++#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET (16)
++#define MMC_CSD_C_SIZE_LSB_MASK (0x0003)
++#define MMC_CSD_C_SIZE_MSB_MASK (0x03FF)
++#define MMC_CSD_C_SIZE_MSB_OFFSET (2)
+
-+/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
-+ * ACTIMA
-+ * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
-+ * TDPL (Twr) = 15/6 = 2.5 -> 3
-+ * TRRD = 12/6 = 2
-+ * TRCD = 18/6 = 3
-+ * TRP = 18/6 = 3
-+ * TRAS = 42/6 = 7
-+ * TRC = 60/6 = 10
-+ * TRFC = 72/6 = 12
-+ * ACTIMB
-+ * TCKE = 2
-+ * XSR = 120/6 = 20
-+ */
-+#define TDAL_165 6
-+#define TDPL_165 3
-+#define TRRD_165 2
-+#define TRCD_165 3
-+#define TRP_165 3
-+#define TRAS_165 7
-+#define TRC_165 10
-+#define TRFC_165 12
-+#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) \
-+ | (TRP_165 << 15) | (TRCD_165 << 12) |(TRRD_165 << 9) | \
-+ (TDPL_165 << 6) | (TDAL_165))
++#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0)
++#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3)
++#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0)
++#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3)
++#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3)
+
-+#define TWTR_165 1
-+#define TCKE_165 2
-+#define TXP_165 2
-+#define XSR_165 20
-+#define V_ACTIMB_165 ((TCKE_165 << 12) | (XSR_165 << 0)) | \
-+ (TXP_165 << 8) | (TWTR_165 << 16)
++typedef struct {
++ unsigned not_used:1;
++ unsigned crc:7;
++ unsigned ecc:2;
++ unsigned file_format:2;
++ unsigned tmp_write_protect:1;
++ unsigned perm_write_protect:1;
++ unsigned copy:1;
++ unsigned file_format_grp:1;
++ unsigned content_prot_app:1;
++ unsigned reserved_1:4;
++ unsigned write_bl_partial:1;
++ unsigned write_bl_len:4;
++ unsigned r2w_factor:3;
++ unsigned default_ecc:2;
++ unsigned wp_grp_enable:1;
++ unsigned wp_grp_size:5;
++ unsigned erase_grp_mult:5;
++ unsigned erase_grp_size:5;
++ unsigned c_size_mult:3;
++ unsigned vdd_w_curr_max:3;
++ unsigned vdd_w_curr_min:3;
++ unsigned vdd_r_curr_max:3;
++ unsigned vdd_r_curr_min:3;
++ unsigned c_size_lsb:2;
++ unsigned c_size_msb:10;
++ unsigned reserved_2:2;
++ unsigned dsr_imp:1;
++ unsigned read_blk_misalign:1;
++ unsigned write_blk_misalign:1;
++ unsigned read_bl_partial:1;
++ unsigned read_bl_len:4;
++ unsigned ccc:12;
++ unsigned tran_speed:8;
++ unsigned nsac:8;
++ unsigned taac:8;
++ unsigned reserved_3:2;
++ unsigned spec_vers:4;
++ unsigned csd_structure:2;
++} mmc_csd_reg_t;
+
-+# define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
-+# define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
-+# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
++/* csd for sd2.0 */
++typedef struct {
++ unsigned not_used:1;
++ unsigned crc:7;
++ unsigned reserved_1:2;
++ unsigned file_format:2;
++ unsigned tmp_write_protect:1;
++ unsigned perm_write_protect:1;
++ unsigned copy:1;
++ unsigned file_format_grp:1;
++ unsigned reserved_2:5;
++ unsigned write_bl_partial:1;
++ unsigned write_bl_len:4;
++ unsigned r2w_factor:3;
++ unsigned reserved_3:2;
++ unsigned wp_grp_enable:1;
++ unsigned wp_grp_size:7;
++ unsigned sector_size:7;
++ unsigned erase_blk_len:1;
++ unsigned reserved_4:1;
++ unsigned c_size_lsb:16;
++ unsigned c_size_msb:6;
++ unsigned reserved_5:6;
++ unsigned dsr_imp:1;
++ unsigned read_blk_misalign:1;
++ unsigned write_blk_misalign:1;
++ unsigned read_bl_partial:1;
++ unsigned read_bl_len:4;
++ unsigned ccc:12;
++ unsigned tran_speed:8;
++ unsigned nsac:8;
++ unsigned taac:8;
++ unsigned reserved_6:6;
++ unsigned csd_structure:2;
++} mmc_sd2_csd_reg_t;
++
++/* extended csd - 512 bytes long */
++typedef struct {
++ unsigned char reserved_1[181];
++ unsigned char erasedmemorycontent;
++ unsigned char reserved_2;
++ unsigned char buswidthmode;
++ unsigned char reserved_3;
++ unsigned char highspeedinterfacetiming;
++ unsigned char reserved_4;
++ unsigned char powerclass;
++ unsigned char reserved_5;
++ unsigned char commandsetrevision;
++ unsigned char reserved_6;
++ unsigned char commandset;
++ unsigned char extendedcsdrevision;
++ unsigned char reserved_7;
++ unsigned char csdstructureversion;
++ unsigned char reserved_8;
++ unsigned char cardtype;
++ unsigned char reserved_9[3];
++ unsigned char powerclass_52mhz_1_95v;
++ unsigned char powerclass_26mhz_1_95v;
++ unsigned char powerclass_52mhz_3_6v;
++ unsigned char powerclass_26mhz_3_6v;
++ unsigned char reserved_10;
++ unsigned char minreadperf_4b_26mhz;
++ unsigned char minwriteperf_4b_26mhz;
++ unsigned char minreadperf_8b_26mhz_4b_52mhz;
++ unsigned char minwriteperf_8b_26mhz_4b_52mhz;
++ unsigned char minreadperf_8b_52mhz;
++ unsigned char minwriteperf_8b_52mhz;
++ unsigned char reserved_11;
++ unsigned int sectorcount;
++ unsigned char reserved_12[288];
++ unsigned char supportedcommandsets;
++ unsigned char reserved_13[7];
++} mmc_extended_csd_reg_t;
++
++/* mmc sd responce */
++typedef struct {
++ unsigned int ocr;
++} mmc_resp_r3;
++
++typedef struct {
++ unsigned short cardstatus;
++ unsigned short newpublishedrca;
++} mmc_resp_r6;
++
++extern mmc_card_data mmc_dev;
++
++unsigned char mmc_lowlevel_init(void);
++unsigned char mmc_send_command(unsigned int cmd, unsigned int arg,
++ unsigned int *response);
++unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd);
++unsigned char mmc_set_opendrain(unsigned char state);
++unsigned char mmc_read_data(unsigned int *output_buf);
+
++#endif /* MMC_H */
+diff --git a/include/asm-arm/arch-omap3/mmc_host_def.h b/include/asm-arm/arch-omap3/mmc_host_def.h
+new file mode 100644
+index 0000000..37aaa08
+--- /dev/null
++++ b/include/asm-arm/arch-omap3/mmc_host_def.h
+@@ -0,0 +1,166 @@
+/*
-+ * GPMC settings -
-+ * Definitions is as per the following format
-+ * # define <PART>_GPMC_CONFIG<x> <value>
-+ * Where:
-+ * PART is the part name e.g. STNOR - Intel Strata Flash
-+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
-+ * Value is corresponding value
++ * (C) Copyright 2008
++ * Texas Instruments, <www.ti.com>
++ * Syed Mohammed Khasim <khasim@ti.com>
+ *
-+ * For every valid PRCM configuration there should be only one definition of
-+ * the same. if values are independent of the board, this definition will be
-+ * present in this file if values are dependent on the board, then this should
-+ * go into corresponding mem-boardName.h file
++ * See file CREDITS for list of people who contributed to this
++ * project.
+ *
-+ * Currently valid part Names are (PART):
-+ * STNOR - Intel Strata Flash
-+ * SMNAND - Samsung NAND
-+ * MPDB - H4 MPDB board
-+ * SBNOR - Sibley NOR
-+ * MNAND - Micron Large page x16 NAND
-+ * ONNAND - Samsung One NAND
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation's version 2 of
++ * the License.
+ *
-+ * include/configs/file.h contains the defn - for all CS we are interested
-+ * #define OMAP34XX_GPMC_CSx PART
-+ * #define OMAP34XX_GPMC_CSx_SIZE Size
-+ * #define OMAP34XX_GPMC_CSx_MAP Map
-+ * Where:
-+ * x - CS number
-+ * PART - Part Name as defined above
-+ * SIZE - how big is the mapping to be
-+ * GPMC_SIZE_128M - 0x8
-+ * GPMC_SIZE_64M - 0xC
-+ * GPMC_SIZE_32M - 0xE
-+ * GPMC_SIZE_16M - 0xF
-+ * MAP - Map this CS to which address(GPMC address space)- Absolute address
-+ * >>24 before being used.
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
+ */
-+#define GPMC_SIZE_128M 0x8
-+#define GPMC_SIZE_64M 0xC
-+#define GPMC_SIZE_32M 0xE
-+#define GPMC_SIZE_16M 0xF
-+
-+# define SMNAND_GPMC_CONFIG1 0x00000800
-+# define SMNAND_GPMC_CONFIG2 0x00141400
-+# define SMNAND_GPMC_CONFIG3 0x00141400
-+# define SMNAND_GPMC_CONFIG4 0x0F010F01
-+# define SMNAND_GPMC_CONFIG5 0x010C1414
-+# define SMNAND_GPMC_CONFIG6 0x1F0F0A80
-+# define SMNAND_GPMC_CONFIG7 0x00000C44
+
-+# define M_NAND_GPMC_CONFIG1 0x00001800
-+# define M_NAND_GPMC_CONFIG2 0x00141400
-+# define M_NAND_GPMC_CONFIG3 0x00141400
-+# define M_NAND_GPMC_CONFIG4 0x0F010F01
-+# define M_NAND_GPMC_CONFIG5 0x010C1414
-+# define M_NAND_GPMC_CONFIG6 0x1f0f0A80
-+# define M_NAND_GPMC_CONFIG7 0x00000C44
-+
-+# define STNOR_GPMC_CONFIG1 0x3
-+# define STNOR_GPMC_CONFIG2 0x00151501
-+# define STNOR_GPMC_CONFIG3 0x00060602
-+# define STNOR_GPMC_CONFIG4 0x11091109
-+# define STNOR_GPMC_CONFIG5 0x01141F1F
-+# define STNOR_GPMC_CONFIG6 0x000004c4
-+
-+# define SIBNOR_GPMC_CONFIG1 0x1200
-+# define SIBNOR_GPMC_CONFIG2 0x001f1f00
-+# define SIBNOR_GPMC_CONFIG3 0x00080802
-+# define SIBNOR_GPMC_CONFIG4 0x1C091C09
-+# define SIBNOR_GPMC_CONFIG5 0x01131F1F
-+# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
-+
-+# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
-+# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
-+# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
-+# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
-+# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
-+# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
++#ifndef MMC_HOST_DEF_H
++#define MMC_HOST_DEF_H
+
-+# define MPDB_GPMC_CONFIG1 0x00011000
-+# define MPDB_GPMC_CONFIG2 0x001f1f01
-+# define MPDB_GPMC_CONFIG3 0x00080803
-+# define MPDB_GPMC_CONFIG4 0x1c0b1c0a
-+# define MPDB_GPMC_CONFIG5 0x041f1F1F
-+# define MPDB_GPMC_CONFIG6 0x1F0F04C4
++/*
++ * OMAP HSMMC register definitions
++ */
++#define OMAP_HSMMC_SYSCONFIG (*(unsigned int *) 0x4809C010)
++#define OMAP_HSMMC_SYSSTATUS (*(unsigned int *) 0x4809C014)
++#define OMAP_HSMMC_CON (*(unsigned int *) 0x4809C02C)
++#define OMAP_HSMMC_BLK (*(unsigned int *) 0x4809C104)
++#define OMAP_HSMMC_ARG (*(unsigned int *) 0x4809C108)
++#define OMAP_HSMMC_CMD (*(unsigned int *) 0x4809C10C)
++#define OMAP_HSMMC_RSP10 (*(unsigned int *) 0x4809C110)
++#define OMAP_HSMMC_RSP32 (*(unsigned int *) 0x4809C114)
++#define OMAP_HSMMC_RSP54 (*(unsigned int *) 0x4809C118)
++#define OMAP_HSMMC_RSP76 (*(unsigned int *) 0x4809C11C)
++#define OMAP_HSMMC_DATA (*(unsigned int *) 0x4809C120)
++#define OMAP_HSMMC_PSTATE (*(unsigned int *) 0x4809C124)
++#define OMAP_HSMMC_HCTL (*(unsigned int *) 0x4809C128)
++#define OMAP_HSMMC_SYSCTL (*(unsigned int *) 0x4809C12C)
++#define OMAP_HSMMC_STAT (*(unsigned int *) 0x4809C130)
++#define OMAP_HSMMC_IE (*(unsigned int *) 0x4809C134)
++#define OMAP_HSMMC_CAPA (*(unsigned int *) 0x4809C140)
+
-+# define P2_GPMC_CONFIG1 0x0
-+# define P2_GPMC_CONFIG2 0x0
-+# define P2_GPMC_CONFIG3 0x0
-+# define P2_GPMC_CONFIG4 0x0
-+# define P2_GPMC_CONFIG5 0x0
-+# define P2_GPMC_CONFIG6 0x0
++/* T2 Register definitions */
++#define CONTROL_DEV_CONF0 (*(unsigned int *) 0x48002274)
++#define CONTROL_PBIAS_LITE (*(unsigned int *) 0x48002520)
+
-+# define ONENAND_GPMC_CONFIG1 0x00001200
-+# define ONENAND_GPMC_CONFIG2 0x000F0F01
-+# define ONENAND_GPMC_CONFIG3 0x00030301
-+# define ONENAND_GPMC_CONFIG4 0x0F040F04
-+# define ONENAND_GPMC_CONFIG5 0x010F1010
-+# define ONENAND_GPMC_CONFIG6 0x1F060000
++/*
++ * OMAP HS MMC Bit definitions
++ */
++#define MMC_SOFTRESET (0x1 << 1)
++#define RESETDONE (0x1 << 0)
++#define NOOPENDRAIN (0x0 << 0)
++#define OPENDRAIN (0x1 << 0)
++#define OD (0x1 << 0)
++#define INIT_NOINIT (0x0 << 1)
++#define INIT_INITSTREAM (0x1 << 1)
++#define HR_NOHOSTRESP (0x0 << 2)
++#define STR_BLOCK (0x0 << 3)
++#define MODE_FUNC (0x0 << 4)
++#define DW8_1_4BITMODE (0x0 << 5)
++#define MIT_CTO (0x0 << 6)
++#define CDP_ACTIVEHIGH (0x0 << 7)
++#define WPP_ACTIVEHIGH (0x0 << 8)
++#define RESERVED_MASK (0x3 << 9)
++#define CTPL_MMC_SD (0x0 << 11)
++#define BLEN_512BYTESLEN (0x200 << 0)
++#define NBLK_STPCNT (0x0 << 16)
++#define DE_DISABLE (0x0 << 0)
++#define BCE_DISABLE (0x0 << 1)
++#define ACEN_DISABLE (0x0 << 2)
++#define DDIR_OFFSET (4)
++#define DDIR_MASK (0x1 << 4)
++#define DDIR_WRITE (0x0 << 4)
++#define DDIR_READ (0x1 << 4)
++#define MSBS_SGLEBLK (0x0 << 5)
++#define RSP_TYPE_OFFSET (16)
++#define RSP_TYPE_MASK (0x3 << 16)
++#define RSP_TYPE_NORSP (0x0 << 16)
++#define RSP_TYPE_LGHT136 (0x1 << 16)
++#define RSP_TYPE_LGHT48 (0x2 << 16)
++#define RSP_TYPE_LGHT48B (0x3 << 16)
++#define CCCE_NOCHECK (0x0 << 19)
++#define CCCE_CHECK (0x1 << 19)
++#define CICE_NOCHECK (0x0 << 20)
++#define CICE_CHECK (0x1 << 20)
++#define DP_OFFSET (21)
++#define DP_MASK (0x1 << 21)
++#define DP_NO_DATA (0x0 << 21)
++#define DP_DATA (0x1 << 21)
++#define CMD_TYPE_NORMAL (0x0 << 22)
++#define INDEX_OFFSET (24)
++#define INDEX_MASK (0x3f << 24)
++#define INDEX(i) (i << 24)
++#define DATI_MASK (0x1 << 1)
++#define DATI_CMDDIS (0x1 << 1)
++#define DTW_1_BITMODE (0x0 << 1)
++#define DTW_4_BITMODE (0x1 << 1)
++#define SDBP_PWROFF (0x0 << 8)
++#define SDBP_PWRON (0x1 << 8)
++#define SDVS_1V8 (0x5 << 9)
++#define SDVS_3V0 (0x6 << 9)
++#define ICE_MASK (0x1 << 0)
++#define ICE_STOP (0x0 << 0)
++#define ICS_MASK (0x1 << 1)
++#define ICS_NOTREADY (0x0 << 1)
++#define ICE_OSCILLATE (0x1 << 0)
++#define CEN_MASK (0x1 << 2)
++#define CEN_DISABLE (0x0 << 2)
++#define CEN_ENABLE (0x1 << 2)
++#define CLKD_OFFSET (6)
++#define CLKD_MASK (0x3FF << 6)
++#define DTO_MASK (0xF << 16)
++#define DTO_15THDTO (0xE << 16)
++#define SOFTRESETALL (0x1 << 24)
++#define CC_MASK (0x1 << 0)
++#define TC_MASK (0x1 << 1)
++#define BWR_MASK (0x1 << 4)
++#define BRR_MASK (0x1 << 5)
++#define ERRI_MASK (0x1 << 15)
++#define IE_CC (0x01 << 0)
++#define IE_TC (0x01 << 1)
++#define IE_BWR (0x01 << 4)
++#define IE_BRR (0x01 << 5)
++#define IE_CTO (0x01 << 16)
++#define IE_CCRC (0x01 << 17)
++#define IE_CEB (0x01 << 18)
++#define IE_CIE (0x01 << 19)
++#define IE_DTO (0x01 << 20)
++#define IE_DCRC (0x01 << 21)
++#define IE_DEB (0x01 << 22)
++#define IE_CERR (0x01 << 28)
++#define IE_BADA (0x01 << 29)
++
++#define VS30_3V0SUP (1 << 25)
++#define VS18_1V8SUP (1 << 26)
+
-+/* max number of GPMC Chip Selects */
-+#define GPMC_MAX_CS 8
-+/* max number of GPMC regs */
-+#define GPMC_MAX_REG 7
++/* Driver definitions */
++#define MMCSD_SECTOR_SIZE (512)
++#define MMC_CARD 0
++#define SD_CARD 1
++#define BYTE_MODE 0
++#define SECTOR_MODE 1
++#define CLK_INITSEQ 0
++#define CLK_400KHZ 1
++#define CLK_MISC 2
+
-+#define PISMO1_NOR 1
-+#define PISMO1_NAND 2
-+#define PISMO2_CS0 3
-+#define PISMO2_CS1 4
-+#define PISMO1_ONENAND 5
-+#define DBG_MPDB 6
-+#define PISMO2_NAND_CS0 7
-+#define PISMO2_NAND_CS1 8
++typedef struct {
++ unsigned int card_type;
++ unsigned int version;
++ unsigned int mode;
++ unsigned int size;
++ unsigned int RCA;
++} mmc_card_data;
+
-+/* make it readable for the gpmc_init */
-+#define PISMO1_NOR_BASE FLASH_BASE
-+#define PISMO1_NAND_BASE NAND_BASE
-+#define PISMO2_CS0_BASE PISMO2_MAP1
-+#define PISMO1_ONEN_BASE ONENAND_MAP
-+#define DBG_MPDB_BASE DEBUG_BASE
++#define mmc_reg_out(addr, mask, val)\
++ (addr) = (((addr)) & (~(mask))) | ((val) & (mask));
++#define mmc_reg_out(addr, mask, val)\
++ (addr) = (((addr)) & (~(mask))) | ((val) & (mask));
+
-+#endif /* endif _MEM_H_ */
-diff --git a/include/asm-arm/arch-omap3/mmc.h b/include/asm-arm/arch-omap3/mmc.h
-new file mode 100644
-index 0000000..f265d8a
---- /dev/null
-+++ b/include/asm-arm/arch-omap3/mmc.h
-@@ -0,0 +1,175 @@
-+/*
-+ * linux/drivers/mmc/mmc_pxa.h
-+ *
-+ * Author: Vladimir Shebordaev, Igor Oblakov
-+ * Copyright: MontaVista Software Inc.
-+ *
-+ * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __MMC_PXA_P_H__
-+#define __MMC_PXA_P_H__
-+
-+/* PXA-250 MMC controller registers */
-+
-+/* MMC_STRPCL */
-+#define MMC_STRPCL_STOP_CLK (0x0001UL)
-+#define MMC_STRPCL_START_CLK (0x0002UL)
-+
-+/* MMC_STAT */
-+
-+#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
-+ |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
-+ |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
-+
-+/* MMC_CLKRT */
-+#define MMC_CLKRT_20MHZ (0x0000UL)
-+#define MMC_CLKRT_10MHZ (0x0001UL)
-+#define MMC_CLKRT_5MHZ (0x0002UL)
-+#define MMC_CLKRT_2_5MHZ (0x0003UL)
-+#define MMC_CLKRT_1_25MHZ (0x0004UL)
-+#define MMC_CLKRT_0_625MHZ (0x0005UL)
-+#define MMC_CLKRT_0_3125MHZ (0x0006UL)
-+
-+/* MMC_SPI */
-+#define MMC_SPI_DISABLE (0x00UL)
-+#define MMC_SPI_EN (0x01UL)
-+#define MMC_SPI_CS_EN (0x01UL << 2)
-+#define MMC_SPI_CS_ADDRESS (0x01UL << 3)
-+#define MMC_SPI_CRC_ON (0x01UL << 1)
-+
-+/* MMC_CMDAT */
-+#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7)
-+#define MMC_CMDAT_INIT (0x0001UL << 6)
-+#define MMC_CMDAT_BUSY (0x0001UL << 5)
-+#define MMC_CMDAT_STREAM (0x0001UL << 4)
-+#define MMC_CMDAT_BLOCK (0x0000UL << 4)
-+#define MMC_CMDAT_WRITE (0x0001UL << 3)
-+#define MMC_CMDAT_READ (0x0000UL << 3)
-+#define MMC_CMDAT_DATA_EN (0x0001UL << 2)
-+#define MMC_CMDAT_R1 (0x0001UL)
-+#define MMC_CMDAT_R2 (0x0002UL)
-+#define MMC_CMDAT_R3 (0x0003UL)
-+
-+/* MMC_RESTO */
-+#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */
-+
-+/* MMC_RDTO */
-+#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */
-+
-+/* MMC_BLKLEN */
-+#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */
-+
-+/* MMC_PRTBUF */
-+#define MMC_PRTBUF_BUF_PART_FULL (0x01UL)
-+#define MMC_PRTBUF_BUF_FULL (0x00UL )
-+
-+/* MMC_I_MASK */
-+#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6)
-+#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5)
-+#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4)
-+#define MMC_I_MASK_STOP_CMD (0x01UL << 3)
-+#define MMC_I_MASK_END_CMD_RES (0x01UL << 2)
-+#define MMC_I_MASK_PRG_DONE (0x01UL << 1)
-+#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL)
-+#define MMC_I_MASK_ALL (0x07fUL)
-+
-+/* MMC_I_REG */
-+#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6)
-+#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5)
-+#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4)
-+#define MMC_I_REG_STOP_CMD (0x01UL << 3)
-+#define MMC_I_REG_END_CMD_RES (0x01UL << 2)
-+#define MMC_I_REG_PRG_DONE (0x01UL << 1)
-+#define MMC_I_REG_DATA_TRAN_DONE (0x01UL)
-+#define MMC_I_REG_ALL (0x007fUL)
-+
-+/* MMC_CMD */
-+#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */
-+#define CMD(x) (x)
-+
-+#define MMC_DEFAULT_RCA 1
-+
-+#define MMC_BLOCK_SIZE 512
-+#define MMC_CMD_RESET 0
-+#define MMC_CMD_SEND_OP_COND 1
-+#define MMC_CMD_ALL_SEND_CID 2
-+#define MMC_CMD_SET_RCA 3
-+#define MMC_CMD_SEND_CSD 9
-+#define MMC_CMD_SEND_CID 10
-+#define MMC_CMD_SEND_STATUS 13
-+#define MMC_CMD_SET_BLOCKLEN 16
-+#define MMC_CMD_READ_BLOCK 17
-+#define MMC_CMD_RD_BLK_MULTI 18
-+#define MMC_CMD_WRITE_BLOCK 24
-+
-+#define MMC_MAX_BLOCK_SIZE 512
-+
-+#define MMC_R1_IDLE_STATE 0x01
-+#define MMC_R1_ERASE_STATE 0x02
-+#define MMC_R1_ILLEGAL_CMD 0x04
-+#define MMC_R1_COM_CRC_ERR 0x08
-+#define MMC_R1_ERASE_SEQ_ERR 0x01
-+#define MMC_R1_ADDR_ERR 0x02
-+#define MMC_R1_PARAM_ERR 0x04
-+
-+#define MMC_R1B_WP_ERASE_SKIP 0x0002
-+#define MMC_R1B_ERR 0x0004
-+#define MMC_R1B_CC_ERR 0x0008
-+#define MMC_R1B_CARD_ECC_ERR 0x0010
-+#define MMC_R1B_WP_VIOLATION 0x0020
-+#define MMC_R1B_ERASE_PARAM 0x0040
-+#define MMC_R1B_OOR 0x0080
-+#define MMC_R1B_IDLE_STATE 0x0100
-+#define MMC_R1B_ERASE_RESET 0x0200
-+#define MMC_R1B_ILLEGAL_CMD 0x0400
-+#define MMC_R1B_COM_CRC_ERR 0x0800
-+#define MMC_R1B_ERASE_SEQ_ERR 0x1000
-+#define MMC_R1B_ADDR_ERR 0x2000
-+#define MMC_R1B_PARAM_ERR 0x4000
-+
-+typedef struct mmc_cid {
-+/* FIXME: BYTE_ORDER */
-+ unsigned char year:4, month:4;
-+ unsigned char sn[3];
-+ unsigned char fwrev:4, hwrev:4;
-+ unsigned char name[6];
-+ unsigned char id[3];
-+} mmc_cid_t;
-+
-+typedef struct mmc_csd {
-+ unsigned char ecc:2,
-+ file_format:2,
-+ tmp_write_protect:1,
-+ perm_write_protect:1, copy:1, file_format_grp:1;
-+ unsigned long int content_prot_app:1,
-+ rsvd3:4,
-+ write_bl_partial:1,
-+ write_bl_len:4,
-+ r2w_factor:3,
-+ default_ecc:2,
-+ wp_grp_enable:1,
-+ wp_grp_size:5,
-+ erase_grp_mult:5,
-+ erase_grp_size:5,
-+ c_size_mult1:3,
-+ vdd_w_curr_max:3,
-+ vdd_w_curr_min:3,
-+ vdd_r_curr_max:3,
-+ vdd_r_curr_min:3,
-+ c_size:12,
-+ rsvd2:2,
-+ dsr_imp:1,
-+ read_blk_misalign:1, write_blk_misalign:1, read_bl_partial:1;
-+
-+ unsigned short read_bl_len:4, ccc:12;
-+ unsigned char tran_speed;
-+ unsigned char nsac;
-+ unsigned char taac;
-+ unsigned char rsvd1:2, spec_vers:4, csd_structure:2;
-+} mmc_csd_t;
-+
-+#endif /* __MMC_PXA_P_H__ */
++#endif /* MMC_HOST_DEF_H */
diff --git a/include/asm-arm/arch-omap3/mux.h b/include/asm-arm/arch-omap3/mux.h
new file mode 100644
-index 0000000..23d5c94
+index 0000000..33947b9
--- /dev/null
+++ b/include/asm-arm/arch-omap3/mux.h
-@@ -0,0 +1,407 @@
+@@ -0,0 +1,757 @@
+/*
-+ * (C) Copyright 2006
++ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
-+#ifndef _OMAP3430_MUX_H_
-+#define _OMAP3430_MUX_H_
++#ifndef _MUX_H_
++#define _MUX_H_
+
+/*
+ * IEN - Input Enable
+#define M6 6
+#define M7 7
+
-+/*
-+ * To get the actual address the offset has to added
-+ * with OMAP34XX_CTRL_BASE to get the actual address
++/*
++ * To get the actual address the offset has to added
++ * with OMAP34XX_CTRL_BASE to get the actual address
+ */
+
+ /*SDRC*/
+#define CONTROL_PADCONF_McBSP2_CLKX 0x013E
+#define CONTROL_PADCONF_McBSP2_DR 0x0140
+#define CONTROL_PADCONF_McBSP2_DX 0x0142
-+#define CONTROL_PADCONF_
+#define CONTROL_PADCONF_MMC1_CLK 0x0144
+#define CONTROL_PADCONF_MMC1_CMD 0x0146
+#define CONTROL_PADCONF_MMC1_DAT0 0x0148
+#define CONTROL_PADCONF_d2d_sbusflag 0x0260
+#define CONTROL_PADCONF_sdrc_cke0 0x0262
+#define CONTROL_PADCONF_sdrc_cke1 0x0264
++
++#define MUX_VAL(OFFSET,VALUE)\
++ __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
++
++#define CP(x) (CONTROL_PADCONF_##x)
++
++/*
++ * IEN - Input Enable
++ * IDIS - Input Disable
++ * PTD - Pull type Down
++ * PTU - Pull type Up
++ * DIS - Pull type selection is inactive
++ * EN - Pull type selection is active
++ * M0 - Mode 0
++ * The commented string gives the final mux configuration for that pin
++ */
++#define MUX_DEFAULT_ES2() \
++ /*SDRC*/\
++ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
++ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
++ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
++ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
++ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
++ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
++ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
++ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
++ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
++ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
++ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
++ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
++ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
++ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
++ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
++ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
++ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
++ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
++ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
++ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
++ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
++ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
++ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
++ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
++ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
++ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
++ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
++ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
++ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
++ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
++ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
++ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
++ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
++ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
++ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
++ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
++ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
++ /*GPMC*/\
++ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
++ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
++ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
++ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
++ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
++ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
++ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
++ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
++ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
++ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
++ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
++ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
++ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
++ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
++ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
++ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
++ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
++ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
++ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
++ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
++ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
++ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
++ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
++ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
++ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
++ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
++ MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
++ MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
++ MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
++ MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
++ /* For Beagle Rev 2 boards*/\
++ MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0))\
++ MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0))\
++ MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1))\
++ MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1))\
++ MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0))\
++ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0))\
++ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0))\
++ /* till here */ \
++ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
++ MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
++ MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
++ MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
++ MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
++ MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
++ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
++ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
++ /*DSS*/\
++ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
++ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
++ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
++ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
++ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
++ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
++ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
++ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
++ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
++ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
++ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
++ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
++ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
++ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
++ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
++ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
++ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
++ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
++ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
++ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
++ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
++ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
++ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
++ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
++ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
++ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
++ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
++ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
++ /*CAMERA*/\
++ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
++ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
++ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
++ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
++ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
++ /* - CAM_RESET*/\
++ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
++ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
++ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
++ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
++ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
++ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
++ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
++ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
++ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
++ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
++ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
++ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
++ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
++ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
++ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
++ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
++ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
++ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
++ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
++ /*Audio Interface */\
++ MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
++ MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
++ MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
++ MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
++ /*Expansion card */\
++ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
++ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
++ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
++ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
++ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
++ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
++ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
++ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
++ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
++ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
++ /*Wireless LAN */\
++ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
++ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
++ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
++ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
++ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
++ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
++ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
++ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
++ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
++ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
++ /*Bluetooth*/\
++ MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
++ MUX_VAL(CP(McBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
++ MUX_VAL(CP(McBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
++ MUX_VAL(CP(McBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
++ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
++ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
++ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
++ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\
++ /*Modem Interface */\
++ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
++ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
++ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
++ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
++ MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
++ MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
++ MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
++ MUX_VAL(CP(McBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
++ MUX_VAL(CP(McBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
++ MUX_VAL(CP(McBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
++ /* - BT_WAKEUP*/\
++ MUX_VAL(CP(McBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
++ MUX_VAL(CP(McBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
++ MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
++ MUX_VAL(CP(McBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
++ MUX_VAL(CP(McBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
++ /*Serial Interface*/\
++ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_*/\
++ /* RCTX*/\
++ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
++ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
++ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
++ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
++ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
++ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
++ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
++ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
++ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
++ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
++ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
++ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
++ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
++ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
++ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
++ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
++ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
++ MUX_VAL(CP(I2C2_SCL), (IDIS | PTU | DIS | M4)) /*GPIO_168*/\
++ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
++ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
++ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
++ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
++ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
++ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
++ MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
++ MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
++ MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
++ MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
++ MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
++ MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
++ /* - NOR_DPD*/\
++ MUX_VAL(CP(McSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\
++ MUX_VAL(CP(McSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
++ MUX_VAL(CP(McSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
++ MUX_VAL(CP(McSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
++ MUX_VAL(CP(McSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
++ MUX_VAL(CP(McSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
++ /*Control and debug */\
++ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
++ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
++ MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
++ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
++ /* - PEN_IRQ */\
++ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
++ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
++ /* - MMC1_WP */\
++ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
++ /* - LCD_ENVDD*/\
++ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
++ /* - LAN_INTR0*/\
++ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
++ /* - MMC2_WP*/\
++ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
++ /* - LCD_ENBKL*/\
++ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
++ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
++ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
++ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
++ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB1_CLK*/\
++ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA0*/\
++ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA1*/\
++ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA2*/\
++ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA7*/\
++ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA4*/\
++ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA5*/\
++ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA6*/\
++ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA3*/\
++ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DIR*/\
++ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_NXT*/\
++ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\
++ MUX_VAL(CP(ETK_D15), (IEN | PTU | EN | M4)) /*GPIO_29*/\
++ MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
++ MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
++ MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
++ MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
++ MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
++ MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
++ MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
++ MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
++ MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
++ MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
++ MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
++ MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
++ MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
++ MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
++ MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
++ MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
++ MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
++ MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
++ MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
++ MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
++ MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
++ MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
++ MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
++ MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
++ MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
++ MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
++ MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
++ MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
++ MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
++ MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
++ MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
++ MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
++ MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
++ MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
++ MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
++ MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
++ MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
++ MUX_VAL(CP(d2d_nrespwron), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
++ MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
++ MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
++ MUX_VAL(CP(d2d_uma2p6fiq), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
++ MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\
++ MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\
++ MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
++ MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
++ MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
++ MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
++ MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
++ MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
++ MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
++ MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
++ MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
++ MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
++ MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
++ MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
++ MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
++ MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
++ MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
++ MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
++ MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
++ MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
++ MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
++ MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
++ MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
++ MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\
++ /* - not used */
+#endif
diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h
new file mode 100644
-index 0000000..e9b494f
+index 0000000..095bb29
--- /dev/null
+++ b/include/asm-arm/arch-omap3/omap3.h
-@@ -0,0 +1,154 @@
+@@ -0,0 +1,131 @@
+/*
-+ * (C) Copyright 2006
++ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ * MA 02111-1307 USA
+ */
+
-+#ifndef _OMAP3430_SYS_H_
-+#define _OMAP3430_SYS_H_
-+
-+#include <asm/arch/sizes.h>
-+
-+/*
-+ * 3430 specific Section
-+ */
++#ifndef _OMAP3_H_
++#define _OMAP3_H_
+
+/* Stuff on L3 Interconnect */
+#define SMX_APE_BASE 0x68000000
+
-+/* L3 Firewall */
-+#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048)
-+#define A_READPERM0 (SMX_APE_BASE + 0x05050)
-+#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058)
-+
+/* GPMC */
+#define OMAP34XX_GPMC_BASE (0x6E000000)
+
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP34XX_CORE_L4_IO_BASE 0x48000000
-+
+#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
-+
+#define OMAP34XX_L4_PER 0x49000000
-+
+#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
+
+/* CONTROL */
+#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE+0x2000)
+
-+/* TAP information dont know for 3430*/
-+#define OMAP34XX_TAP_BASE (0x49000000) /*giving some junk for virtio */
-+
+/* UART */
+#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE+0x6a000)
+#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE+0x6c000)
+#define OMAP34XX_GPIO5_BASE 0x49056000
+#define OMAP34XX_GPIO6_BASE 0x49058000
+
-+/*
-+ * SDP3430 specific Section
-+ */
-+
-+/*
-+ * The 343x's chip selects are programmable. The mask ROM
-+ * does configure CS0 to 0x08000000 before dispatch. So, if
-+ * you want your code to live below that address, you have to
-+ * be prepared to jump though hoops, to reset the base address.
-+ * Same as in SDP3430
-+ */
-+#if (CONFIG_3430SDP)
-+
-+/* base address for indirect vectors (internal boot mode) */
-+#define SRAM_OFFSET0 0x40000000
-+#define SRAM_OFFSET1 0x00200000
-+#define SRAM_OFFSET2 0x0000F800
-+#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
-+
-+#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
-+
-+/* FPGA on Debug board.*/
-+#define ETH_CONTROL_REG (DEBUG_BASE+0x30b)
-+#define LAN_RESET_REGISTER (DEBUG_BASE+0x1c)
-+
-+#define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60)
-+#define LED_REGISTER (DEBUG_BASE+0x40)
-+#define FPGA_REV_REGISTER (DEBUG_BASE+0x10)
-+#define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800)
-+#define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900)
-+#define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00)
-+#define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00)
-+#define ENHANCED_UI_EE_NAME "750-2075"
-+
-+#elif (CONFIG_OMAP3_BEAGLE)
-+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_OFFSET0 0x40000000
+#define SRAM_OFFSET1 0x00200000
+#define SRAM_OFFSET2 0x0000F800
-+#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
++#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|\
++ SRAM_OFFSET2)
+
+#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
+
+#define DEBUG_LED1 149 /* gpio */
+#define DEBUG_LED2 150 /* gpio */
+
-+#endif /* endif (CONFIG_3430SDP) */
-+
-+#endif
-diff --git a/include/asm-arm/arch-omap3/sizes.h b/include/asm-arm/arch-omap3/sizes.h
-new file mode 100644
-index 0000000..c47320e
---- /dev/null
-+++ b/include/asm-arm/arch-omap3/sizes.h
-@@ -0,0 +1,49 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+/* Size defintions
-+ * Copyright (C) ARM Limited 1998. All rights reserved.
-+ */
-+
-+#ifndef __sizes_h
-+#define __sizes_h 1
-+
-+/* handy sizes */
-+#define SZ_1K 0x00000400
-+#define SZ_4K 0x00001000
-+#define SZ_8K 0x00002000
-+#define SZ_16K 0x00004000
-+#define SZ_32K 0x00008000
-+#define SZ_64K 0x00010000
-+#define SZ_128K 0x00020000
-+#define SZ_256K 0x00040000
-+#define SZ_512K 0x00080000
-+
-+#define SZ_1M 0x00100000
-+#define SZ_2M 0x00200000
-+#define SZ_4M 0x00400000
-+#define SZ_8M 0x00800000
-+#define SZ_16M 0x01000000
-+#define SZ_31M 0x01F00000
-+#define SZ_32M 0x02000000
-+#define SZ_64M 0x04000000
-+#define SZ_128M 0x08000000
-+#define SZ_256M 0x10000000
-+#define SZ_512M 0x20000000
-+
-+#define SZ_1G 0x40000000
-+#define SZ_2G 0x80000000
-+
-+#endif /* __sizes_h */
-diff --git a/include/asm-arm/arch-omap3/sys_info.h b/include/asm-arm/arch-omap3/sys_info.h
-new file mode 100644
-index 0000000..c839e01
---- /dev/null
-+++ b/include/asm-arm/arch-omap3/sys_info.h
-@@ -0,0 +1,74 @@
-+/*
-+ * (C) Copyright 2006
-+ * Texas Instruments, <www.ti.com>
-+ * Richard Woodruff <r-woodruff2@ti.com>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#ifndef _OMAP34XX_SYS_INFO_H_
-+#define _OMAP34XX_SYS_INFO_H_
-+
+#define XDR_POP 5 /* package on package part */
+#define SDR_DISCRETE 4 /* 128M memory SDR module */
+#define DDR_STACKED 3 /* stacked part on 2422 */
-+#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */
++#define DDR_COMBO 2 /* combo part on cpu daughter card */
+#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
+
+#define DDR_100 100 /* type found on most mem d-boards */
+#define CPU_3430_ES1 1
+#define CPU_3430_ES2 2
+
-+/* Currently Virtio models this one */
-+#define CPU_3430_CHIPID 0x0B68A000
-+
-+#define GPMC_MUXED 1
-+#define GPMC_NONMUXED 0
-+
-+#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */
-+#define TYPE_NOR 0x000
-+#define TYPE_ONENAND 0x800
-+
+#define WIDTH_8BIT 0x0000
+#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
+
-+#define I2C_MENELAUS 0x72 /* i2c id for companion chip */
-+#define I2C_TRITON2 0x4B /* addres of power group */
-+
-+#define BOOT_FAST_XIP 0x1f
-+
+/* SDP definitions according to FPGA Rev. Is this OK?? */
+#define SDP_3430_V1 0x1
+#define SDP_3430_V2 0x2
+#endif
diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h
new file mode 100644
-index 0000000..b62bc9f
+index 0000000..271b554
--- /dev/null
+++ b/include/asm-arm/arch-omap3/sys_proto.h
-@@ -0,0 +1,66 @@
+@@ -0,0 +1,64 @@
+/*
-+ * (C) Copyright 2004-2006
++ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
-+#ifndef _OMAP34XX_SYS_PROTO_H_
-+#define _OMAP34XX_SYS_PROTO_H_
++#ifndef _SYS_PROTO_H_
++#define _SYS_PROTO_H_
+
+void prcm_init(void);
+void per_clocks_enable(void);
+void do_sdrc_init(u32, u32);
+void gpmc_init(void);
+
-+void ether_init(void);
+void watchdog_init(void);
+void set_muxconf_regs(void);
+
+u32 get_gpmc0_width(void);
+u32 get_board_type(void);
+void display_board_info(u32);
-+void update_mux(u32, u32);
+u32 get_sdr_cs_size(u32 offset);
+u32 running_in_sdram(void);
+u32 running_in_sram(void);
+#endif
diff --git a/include/configs/omap3530beagle.h b/include/configs/omap3530beagle.h
new file mode 100644
-index 0000000..03dc31b
+index 0000000..fd21ab3
--- /dev/null
+++ b/include/configs/omap3530beagle.h
-@@ -0,0 +1,285 @@
+@@ -0,0 +1,292 @@
+/*
-+ * (C) Copyright 2006
++ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
-+ * Configuration settings for the 3430 TI SDP3430 board.
++ * Configuration settings for the TI OMAP3530 Beagle board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
++#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+#define CONFIG_DOS_PARTITION 1
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
++#include <asm/arch/omap3.h>
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+/*
+ * Size of malloc() pool
+ */
-+#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */
++#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K)
-+#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
++#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+#define CFG_NAND_WP
+
+#define CONFIG_JFFS2_NAND
-+#define CONFIG_JFFS2_DEV "nand0" /* nand device jffs2 lives on */
-+#define CONFIG_JFFS2_PART_OFFSET 0x680000 /* start of jffs2 partition */
++/* nand device jffs2 lives on */
++#define CONFIG_JFFS2_DEV "nand0"
++/* start of jffs2 partition */
++#define CONFIG_JFFS2_PART_OFFSET 0x680000
+#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 10
+
-+#define CONFIG_BOOTCOMMAND \
-+ "mmcinit;fatload mmc 0 0x80300000 uImage; fatload mmc 0 0x81600000 rd-ext2.bin; bootm 0x80300000\0"
++#define CONFIG_BOOTCOMMAND "mmcinit;fatload mmc 0 0x80300000 uImage; fatload mmc 0 0x81600000 rd-ext2.bin; bootm 0x80300000\0"
+
+#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 ramdisk_size=3072 root=/dev/ram0 rw rootfstype=ext2 initrd=0x81600000,3M "
+
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */
-+#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+SZ_31M)
++#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+0x01F00000) /* 31MB */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
-+#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */
++#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */
+
+/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+#endif
+
+
-+#define WRITE_NAND_COMMAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD))
-+#define WRITE_NAND_ADDRESS(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR))
++#define WRITE_NAND_COMMAND(d, adr)\
++ __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD))
++#define WRITE_NAND_ADDRESS(d, adr)\
++ __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR))
+#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT))
+#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT))
+
+/* Other NAND Access APIs */
-+#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
-+#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
++#define NAND_WP_OFF()\
++ do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
++#define NAND_WP_ON()\
++ do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+#define NAND_WAIT_READY(nand) udelay(10)
projects / vuplus_openembedded / commitdiff